1. Digital System Design EEE344 Lecture 3 Introduction to Verilog HDL Prepared by: Engr. Qazi Zia, Assistant Professor EED, COMSATS Attock1

2. CONTENTS  Logic Values  Nets  Registers  Variable Declaration  Constants  Four Levels of Abstraction

3. Logic Values  A bit in verilog may contain 4 values: 20’b 0011_1010_101x_x0z0_011z

4. Nets  Nets are physical connections between components.  The net data types are wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1 and trireg.  Commonly used net is wire wire c // simple wire wand d; assign d = a; // value of d is the logical AND of assign d = b; // a and b

5. Registers  A register type variable is denoted by reg. Other registers are integer, time and real

6. Variable Declaration wire signed [ ] ; The range is declared as [Most Significant bit (MSb): Least Significant bit (LSb)]. reg signed [ ] ;

7. .. Memory declaration: reg [ ] [ : ]; A variable of type reg can also be initialised as: reg x1 =1’b0; // 1-bit reg variable x1 initialize to 0 at declaration Examples

8. Constants

9. Four Levels of Abstraction  switch level  gate level  dataflow level  behavioral or algorithmic level.

10. Switch Level  The code consists of transistors primitives  Not used in practical designing

11. Gate Level or Structural Modeling  The code is composed of verilog gate primitives

13. Dataflow Level  It higher level than gate level  The code contain Expressions, operands and operators  Example assign c = a + b;  The value on wire c is continuously driven by the result of the arithmetic operation.  This assignment statement is also called ‘continuous assignment’. In this statement the right hand side must be a variable of type wire, whereas the operands on the left hand side may be of type wire or reg.

15. Arithmetic Operators

16. Conditional Operators examples 1. assign out = sel ? a : b; 2. assign out = sel[1] ? ( sel[0] ? in3 : in2 ) : ( sel[0] ? in1 : in0 );

17. Concatenation and Replication Operators

18. Replication  A replication operator simply replicates a signal multiple times. Example A 2’b01; B {4{A}} // the replication operator. The operator replicates A four times and assigns the replicated value to B. Thus B = 8’b 01010101.

19. Logical Operators They operate on logical operands and result in a logical TRUE or FALSE A= 4; B=0; A&&B= 0, A ||B= 1 Any value that is not equal 0 is considered as 1 If any operand bit is x or z it is considered as x and that operand is treated as 0 by simulator

20. Logic and Arithmetic Shift Operators Arithmetic Shift right: It Shifts right specified number of bits, fill with value of sign bit if expression is signed, otherwise fill with zero. Arithmetic Shift left: It shifts left specified number of bits and fill with zero.

21. Logical shift example If we want to shift logically A= 6’b101111 by 2: assign B = A >> 2; This drops two LSBs and appends two zeros at the MSB position, thus: B is 6’b001011

22. Arithmetic shift example assign B = A >>> 2; This operation will drop two LSBs and appends the sign bit to two MSB locations. Thus B is 6’b111011.

23. Relational Operators

24. Reduction Operators.

25. example  Apply the & reduction operator to a 4-bit number A=4’b1011: assign out= &A;  This operation is equivalent to performing a bitwise & operation on all the bits of A: out = A[0] & A[1] & A[2] & A[3];

26. Bitwise Arithmetic Operators

27. If we perform bitwise | (or) operation on two 4-bit numbers A = 4’b1011 and B=4b0011. The Verilog expression computes a 4-bit C:  assign C = A | B; This performs the OR operation on corresponding bits of A and B and the operation is equivalent to: C[0] =A[0] | B[0] C[1] =A[1] | B[1] C[2] =A[2] | B[2] C[3] =A[3] | B[3]

28. Equality Operators  While comparing A=4’b101x and B=4’b101x using == and===, out = (A==B) will be x and out = (A===B) will be 1

29. Example 1

31. Results verification

32. Example 2

34. Result verification

35. Block diagram

36. Behavioral Level  The behavioral level is the highest level of abstraction in Verilog.  This level provides high level language constructs like for, while, repeat, if else and case.  Verilog restricts all the behavioral statements to be enclosed in a procedural block.

37. Behavioral Level  In a procedural block all variables on the left hand side of the statements must be declared as of type reg, whereas operands on the right hand side in expressions may be of type reg or wire.  There are two types of procedural block, always and initial.

38. Initial Procedural Block  The initial block executes only once, starting at t=0 simulation time  The characteristics of an initial block are as follows. This block starts with the initial keyword. If multiple statements are used in the block, they are enclosed within begin and end constructs

39. This block is non synthesizable. This block is used only in a stimulus. There are usually more than one initial blocks in the stimulus. All initial blocks execute concurrently in arbitrary order, starting at simulation time 0. The simulator kernel executes the initial block until the execution comes to a #delay operator. Then the execution is suspended and the simulator kernel places the execution of this block in the event list for delay time units in the future. After completing delay time units, the execution is resumed where it was left off.

40. Always block  An always block executes continuously at t=0 and repeatedly thereafter.  An always block is synthesizable provided it adheres to coding guidelines for synthesis.  From the perspective of its execution in a simulator, an always block behaves like an initial block except that, once it ends, it starts repeating itself.

41. Format of writing procedural blocks

42. Blocking and Non-blocking Procedural Assignments  Blocking assignment is represented by = in an always block.  The = blocks further statements from execution. Example always @ (a or b) begin c=a && b; d= a || b; end c= a &&b will first complete its execution then d= a || b; will be executed

43. Non-blocking  In contrast to blocking procedural assignments, non blocking procedural assignments do not block other statements in the block and these statements execute in parallel.  The simulator executes this functionality by assigning the output of these statements to temporary variables, and at the end of execution of the block these temporary variables are assigned to actual variables.

44. Sensitivity list styles

45. Example

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