VLSI Layout Algorithms CSE 6404 A 46 B 65 C 11 D 56 E 23 F 8 H 37 G 19 I 12J 14 K 27 X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Dr. Md. Saidur Rahman

Text Books Algorithms for VLSI Physical Design Automation by Naveed Sherwani Planar Graph Drawing by Takao Nishizeki and Md. Saidur Rahman Physical Design Automation: Theory and Practice by S. M. Sait and H. Youssef

Marks Distribution Attendance 15 Presentation / Class Lecture 25 Discussions on Class Lecture 5 Examination 55

Presentation A paper (or a chapter of a book) from the area of VLSI Layout Algorithms will be assigned to you. You have to read, understand and present the paper. Use PowerPoint slides for presentation. Collect journal papers in the area of VLSI layout algorithms from library or internet

Presentation Format  Problem definition  Results of the paper  Contribution of the paper in respect to previous results  Algorithm and methodology including outline of the proofs  Future works, open problems and your idea

Presentation Schedule Presentation/ Lecture time: 30 minutes Presentation will start from 3rd week. Multi-layer Channel Routing: Complexity and Algorithms by Rajat K. Pal

Objectives General understanding of ICs and their production process. Study the basic algorithms used in designing the layout of a chip.

mannual automation System specificationchip  Large number of devices  Optimization required for high performances  Time-to-market competetion  Cost Why are algorithms needed?

K 10K 100K 1M 10M Transistors Pentium Pro Pentium PPC601 PPC603 MIPS R4000 Microprocessors

Clock speed GHz On-chip, local clock, high performance On-chip, global clock, high performance

Increasing Device and Context Complexity Exponential increase in device complexity More complex system contexts Require exponential increases in design productivity [©Keutzer] We have exponentially more transistors! Complexity

Deep Submicron Effects Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: –Cross­coupled capacitances –Resistance –Inductance [©Keutzer] Design of each transistor is getting more difficult! DSM Effects

Heterogeneity on Chip Greater diversity of on­chip elements –Processors –Software –Memory –Analog [©Keutzer] More transistors doing different things! Heterogeneity

Stronger Market Pressures Less tolerance for design revisions [©Keutzer] Time-to-market Exponentially more complex, greater design risk, greater variety!

A Quadruple­Whammy [©Keutzer] Time-to-market Complexity DSM Effects Heterogeneity

Productivity gap How Are We Doing? [©Keutzer] Source: SEMATECH Productivity Trans. / Staff. Month ,000 10, ,000 1,000,000 10,000, ,000,000 Tr./S.M Logic transistors per chip (K) ,000 10, ,000 1,000,000 10,000,000 Logic Tr./Chip % / Yr. compound complexity growth rate 21% / Yr. compound productivity growth rate We need efficient design algorithms to reduce the production gap.

LAYOUT Geometric description of a circuit A layout consists of set of planar geometric shapes in several layer. Physical design process The process of converting the specification of an electrical circuit into a layout is called physical design process.

VLSI Physical Design Automaion VLSI physical design automation is essentially the study of algorithms and data structures related to physical design process.

VLSI Design Cycle

System Specifications High-level Description Market requirements Cost Technology compromise  Performance  Functionality  Physical dimension  Fabrication technology  Design techniques Factors considered

Specifications High-level Description Functional Description Figs. [©Sherwani]

Packaging Fabri- cation Physical Design Technology Mapping Synthesis Specifications High-level Description Functional Description Placed & Routed Design X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani] Gate-level Design Gate-level Design Logic Description

Placed & Routed Design Packaging Fabri- cation Physical Design Technology Mapping Synthesis Specifications High-level Description Functional Description X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani] Gate-level Design Gate-level Design Logic Description

Physical Design Physical design converts a circuit description into geometric description. This geometric description is used to manufacture a chip. Physical design cycle consists of 1.Partioning 2.Floorplannig and placement 3.Routing 4.Compaction

Design Styles

Full Custom Design Example A/D PLA I/O comp RAM Metal1 Via Metal2 I/O Pad (standard cell design) [©Sherwani]

ASIC (Standard Cell) Design Example D C C B A CC D C D B B C C C Cell Metal1 Metal2 GNDVDD C D A B Cell library Placement [©Sherwani]