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EE 5301 – VLSI Design Automation I Part I: Introduction
Fall 2008 EE VLSI Design Automation I
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Administrative issues
Class Time and venue: MW 12:20pm – 1:35pm, ME 108 Web page: Textbook: Sadiq M. Sait, Habib Youssef, "VLSI Physical Design Automation: Theory and Practice", World Scientific Publishing Company,1999. Grades 30% homework (~5 homeworks) 20% each, two midterms Tentative dates: Mon Oct 22, Wed Nov 26 30% mini-projects (~2 mini-projects) Includes oral presentation for the second Programming required! Fall 2008 EE VLSI Design Automation I
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Administrative issues (contd.)
Personnel Instructor: Sachin Sapatnekar Phone: (612) Office: EE/CSci Office hours: MW 11am-noon, or by appointment TA: TBD Phone: (612) 62x xxxx Office: x-xxx EE/CSci Office hours: TBD, or by appointment Fall 2008 EE VLSI Design Automation I
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Administrative issues (cont.)
Policies Electronic submission of homework preferred Must be received by the due date If you submit a hardcopy, it must be in before class starts You will lose 10% of the total score for each day or part thereof Example: If the HW is graded out of 100 and you are 30 hours late, you automatically lose 20 points Zero tolerance for cheating Collaboration OK, copying NOT OK No extra work for extra credit Check class web pages regularly, students are responsible for checking discussion threads and announcements regularly Subscribe to the class mailing list (instructions on the web page) Fall 2008 EE VLSI Design Automation I
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This is a sample text, not printed, but animated
Online slides Slides are posted on the web Handouts posted as .pdf files Powerpoint slides provided too NOTE: some slides are animated (like this one) Click on the slide to see the animation Click once more. Some slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see) This is a sample text, not printed, but animated Fall 2008 EE VLSI Design Automation I
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What is this course all about?
Prerequisite C / C++ programming experience What is covered? Basic algorithms, complexity theory Integrated circuit (IC) Design flow Computer Aided Design (CAD) tool development for Very Large Scale Integration (VLSI) Lots of programming! Next slides: Overview of IC design steps Related courses at U of M Outline of this course Fall 2008 EE VLSI Design Automation I
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The overall IC industry
Fall 2008 EE VLSI Design Automation I
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EE 5301 - VLSI Design Automation I
IC products Processors CPU, DSP, Controllers Memory chips RAM, ROM, EEPROM Analog Mobile communication, audio/video processing Programmable PLA, FPGA Embedded systems Used in cars, factories Network cards System-on-chip (SoC) Boom! Fall 2008 EE VLSI Design Automation I
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The inverted pyramid Electronic Systems > $1 Trillion
Semiconductor > $220 B CAD $4 B Fall 2008 EE VLSI Design Automation I [©Keutzer]
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Semiconductor industry growth rates
Source: (McClean Report) Fall 2008 EE VLSI Design Automation I [©Bazargan]
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Source: http://www.edat.com/edac
More demand for EDA CAE = Computer Aided Engineering Source: Fall 2008 EE VLSI Design Automation I [©Bazargan]
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Source: http://www.edat.com/edac
Growth in system size CAGR = Compound Annual Growth Rate Source: Fall 2008 EE VLSI Design Automation I [©Bazargan]
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Evolution of the transistor
( Transistor Early IC Vacuum tube Modern IC Fall 2008 EE VLSI Design Automation I
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Acronyms, acronyms everywhere..
SSI (small scale integration) MSI (medium scale integration) LSI (large scale integration) VLSI (very large scale integration) … Fall 2008 EE VLSI Design Automation I
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Example: Intel processor sizes
Silicon Process Technology Intel386TM DX Processor Intel486TM DX Pentium® Processor Pentium® Pro & Pentium® II Processors Source: Fall 2008 EE VLSI Design Automation I
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EE 5301 - VLSI Design Automation I
Moore’s law [intel.com] Fall 2008 EE VLSI Design Automation I
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The Moore’s law article
Electronics, Vol. 38, No. 8, Apr 19, 1965 Fall 2008 EE VLSI Design Automation I
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EE 5301 - VLSI Design Automation I
Feature size trends Recent history 0.8m0.5m0.35m0.25m0.18m0.13m90nm 65nm45nm Projected technologies 32nm22nm16nm 0.7x per generation, 0.5x every two generations [R. Saleh] Fall 2008 EE VLSI Design Automation I
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Starting up a technology node
Fall 2008 EE VLSI Design Automation I
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EE 5301 - VLSI Design Automation I
The International Technology Roadmap for Semiconductors (ITRS) [public.itrs.org] Year Tech Node (nm) Num of Tran Num Wire Level f (MHz) Vdd (V) Power (W) 2001 130 97M 8 1.7 1.2 2003 100 153M 3.1 1.0 150 2005 80 243M 10 5.2 0.9 170 2007 65 386M 6.7 0.7 190 2010 45 773M 11.5 0.6 218 2013 32 1.55G 11 19.3 0.5 251 2016 22 3.09G 28.8 0.4 288 Fall 2008 EE VLSI Design Automation I
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ITRS: Chip frequencies
Clock speed GHz 11 9 7 5 3 1 1997 1999 2001 2003 2006 2009 2012 On-chip, local clock, high performance On-chip, global clock, high performance Fall 2008 EE VLSI Design Automation I [©Keutzer]
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The role of design automation
Fall 2008 EE VLSI Design Automation I
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Tera-scale integration effects
Exponential increase in device complexity Increasing with Moore's law (or faster)! More complex system contexts System contexts in which devices are deployed (e.g. cellular radio) are increasing in complexity Require exponential increases in design productivity Complexity We have exponentially more transistors! Fall 2008 EE VLSI Design Automation I [©Keutzer]
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Nanometer-scale effects
Smaller geometries are causing a wide variety of effects that we have largely ignored in the past: Crosscoupled capacitances Signal integrity Wire resistance effects Wire inductance effects Increased leakage Quantum effects Reliability problems… DSM Effects Design of each transistor is getting more difficult! Fall 2008 EE VLSI Design Automation I [©Keutzer]
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Heterogeneity on chip Greater diversity of onchip elements
Processors Software Memory Analog “more than Moore” technologies Heterogeneity More transistors doing different things! Fall 2008 EE VLSI Design Automation I [©Keutzer]
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Stronger market pressures
Decreasing design window Lower tolerance for design revisions Time-to-market Exponentially more complex, greater design risk, greater variety, and a smaller design window! Fall 2008 EE VLSI Design Automation I [©Keutzer]
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EE 5301 - VLSI Design Automation I
A QuadrupleWhammy integration Tera-scale Time-to-market Heterogeneity Nanometer-scale Effects Fall 2008 EE VLSI Design Automation I [©Keutzer]
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Role of EDA: close the productivity gap
How are we doing? Logic transistors per chip (K) 10 100 1,000 10,000 100,000 1,000,000 10,000,000 Logic Tr./Chip Trans. / Staff . Month Productivity 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Tr./S.M 58% / Yr. compound complexity growth rate Productivity gap 21% / Yr. compound productivity growth rate 1981 1985 1989 1993 1997 2001 2005 2009 Source: SEMATECH Role of EDA: close the productivity gap Fall 2008 EE VLSI Design Automation I [©Keutzer]
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Evolution of the EDA industry
What’s next? Results (design productivity) Synthesis – Cadence, Synopsys Schematic entry – Daisy, Mentor, Valid Transistor entry – Calma, Computervision, Magic Effort (EDA tool effort) McKinsey S-Curve Fall 2008 EE VLSI Design Automation I [©Keutzer]
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EE 5301 - VLSI Design Automation I
The IC design cycle Fall 2008 EE VLSI Design Automation I
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IC design steps (cont.) High-level Description Functional Description
Specifications Behavioral VHDL, C Structural VHDL Fall 2008 EE VLSI Design Automation I Figs. [©Sherwani]
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IC design steps (contd.)
High-level Description Functional Description Specifications Logic Description Synthesis Physical Design Technology Mapping Placed & Routed Design Gate-level Design Fabri- cation X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Packaging Fall 2008 EE VLSI Design Automation I Figs. [©Sherwani]
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The big picture: IC design methods
Cost / Development Time Design Methods Quality # Companies involved Full Custom Standard Cell Library Design ASIC – Standard Cell Design RTL-Level Design Fall 2008 EE VLSI Design Automation I [©Bazargan]
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Optimization: Levels of abstraction
Algorithmic Encoding data, computation scheduling, balancing delays of components, etc. Gate-level Reduce fan-out, capacitance Gate duplication, buffer insertion Layout / Physical-Design Move cells/gates around to shorten wires on critical paths Abut rows to share power / ground lines Effectiveness Level of detail Fall 2008 EE VLSI Design Automation I [©Bazargan]
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Layouts [© Prentice Hall]
Full custom design Component Design Structural/RTL Description Mem Ctrl Comp. Unit Reg File Place & Route A/D PLA I/O comp RAM ... Floorplan [©Sherwani] Layouts [© Prentice Hall] Fall 2008 EE VLSI Design Automation I
![Layouts [© Prentice Hall]](http://slideplayer.com/slide/5260402/16/images/35/Layouts+%5B%C2%A9+Prentice+Hall%5D.jpg "Full custom design. Component Design. Structural/RTL Description. Mem. Ctrl. Comp. Unit. Reg File. Place & Route. A/D. PLA. I/O. comp. RAM. ... Floorplan [©Sherwani] Layouts [© Prentice Hall] Fall EE VLSI Design Automation I.")
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Full custom design example (simplified)
I/O Pad Via comp PLA Metal2 Macro cell design I/O Metal1 RAM A/D Glue logic (standard cell design) [©Sherwani] Fall 2008 EE VLSI Design Automation I
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EE 5301 - VLSI Design Automation I
ASIC design Structural/ RTL Description Mem Ctrl Comp. Unit Reg File HDL Programming P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0'; add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o); Mult_i1 <= sum_o(7 downto 0); D C B A C D A B Cell library Floorplan [©Sherwani] Fall 2008 EE VLSI Design Automation I
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ASIC (Standard Cell) design example (simplified)
GND VDD Metal1 Metal2 D C B A C D A B Cell library Placement [©Sherwani] Fall 2008 EE VLSI Design Automation I
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How does this course fit into the curriculum?
VLSI related courses: VLSI CAD VLSI Design Others EE 5301 VLSI Design Automation I EE 5302 Automation II EE 5323 VLSI Design I EE 5324 VLSI Design II EE 4301 Digital Design With Programmable Logic EE 5329 VLSI Digital Signal Processing Systems EE 5333 Analog Integrated Circuit Design EE 5549 Digital Signal Processing Structures for VLSI Fall 2008 EE VLSI Design Automation I
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EE 5301 - VLSI Design Automation I
Course outline Basic algorithms and complexity theory Circuit representations Classes of problems (P, NP) Classes of algorithms (dynamic programming, network flow, greedy, linear programming, etc.) Graph algorithms Fall 2008 EE VLSI Design Automation I [©Bazargan]
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Course outline (contd.)
Global / detailed routing Maze routing, line-search, Steiner trees, etc. Partitioning FM, KL, hMetis algorithms Floorplanning Slicing, non-slicing floorplans Simulated annealing floorplanning algorithms Placement / Packing Force-directed Simulated annealing Quadratic placement Fall 2008 EE VLSI Design Automation I [©Bazargan]
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EE 5301 - VLSI Design Automation I
To Probe Further... International Technology Roadmap for Semiconductors (ITRS) SEMATECH Textbook Chapter 1 Fall 2008 EE VLSI Design Automation I [©Bazargan]
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