1. Fall 2006EE 5301 - VLSI Design Automation I I-1 EE 5301 – VLSI Design Automation I Kia Bazargan University of Minnesota Part I: Introduction

2. Fall 2006EE 5301 - VLSI Design Automation I I-2 Administrative Issues Class  Time and venue: _MW 4:40pm - 5:55pm, ME212 _  Web page: ohttp://www.ece.umn.edu/users/kia/Courses/EE5301 ohttp://webct.umn.edu/ (requires x.500 ID & pwd) o!!!! Check the class web page & discussion group regularly !!!!  Textbook: Sadiq M. Sait, Habib Youssef, "VLSI Physical Design Automation: Theory and Practice", World Scientific Publishing Company; 1st edition (November 15, 1999) Grades  30% homework  10% presentations / papers  10% quizzes  40% two open book midterms: Mon Oct 16, Wed Nov 29  10% Final project. Due Wed Dec 6

3. Fall 2006EE 5301 - VLSI Design Automation I I-3 Administrative Issues (cont.) Personnel  Instructor: Kia Bazargan oEmail: kia@ece.umn.edu oPhone: (612) 625-4588 oOffice: EE/CSci 4-159 oOffice hours: __MW 3:30-4:30pm __  TA: ___________________ oEmail: ___________________________ oPhone: _____________________________ oOffice: ______________________________ oOffice hours: __________________________

4. Fall 2006EE 5301 - VLSI Design Automation I I-4 Administrative Issues (cont.) Policies  Homework must be received before class starts (hardcopy) or before 4:30pm (electronic) on the due date oThree days of grace period for the whole semester oAfter the grace period is used, > 10 minutes late  0% of the grade  Zero tolerance for cheating  Collaboration OK, copying NOT OK  Include ID on all homework, exams, etc.  No extra work for extra credit  Check class web pages regularly, students are responsible for checking discussion threads and announcements regularly  Subscribe to the class mailing list (instructions on the web page)

5. Fall 2006EE 5301 - VLSI Design Automation I I-5 Online Slides Slides are posted on the web  Handouts posted as.pdf files  Powerpoint slides provided too oNOTE: some slides are animated (like this one) oClick on the slide to see the animation oClick once more. oNote: some slides have notes! (like this one) oSome slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see) This is a sample text, not printed, but animated

6. Fall 2006EE 5301 - VLSI Design Automation I I-6 References and Copyright Textbooks referred (none required)  [Mic94] G. De Micheli “Synthesis and Optimization of Digital Circuits” McGraw-Hill, 1994.  [CLR90] T. H. Cormen, C. E. Leiserson, R. L. Rivest “Introduction to Algorithms” MIT Press, 1990.  [Sar96] M. Sarrafzadeh, C. K. Wong “An Introduction to VLSI Physical Design” McGraw-Hill, 1996.  [She99] N. Sherwani “Algorithms For VLSI Physical Design Automation” Kluwer Academic Publishers, 3 rd edition, 1999.

7. Fall 2006EE 5301 - VLSI Design Automation I I-7 References and Copyright (cont.) Slides used: (Modified by Kia when necessary)  [©Sarrafzadeh] © Majid Sarrafzadeh, 2001; Department of Computer Science, UCLA  [©Sherwani] © Naveed A. Sherwani, 1992 (companion slides to [She99])  [©Keutzer] © Kurt Keutzer, Dept. of EECS, UC-Berekeley http://www-cad.eecs.berkeley.edu/~niraj/ee244/index.htm  [©Gupta] © Rajesh Gupta UC-Irvine http://www.ics.uci.edu/~rgupta/ics280.html

8. Fall 2006EE 5301 - VLSI Design Automation I I-8 What is This Course All About? Prerequisite  C / C++ programming experience  Kia will try to provide tutorials What is covered?  Basic algorithms, complexity theory  Integrated circuit (IC) Design flow  Computer Aided Design (CAD) tool development for Very Large Scale Integration (VLSI)  Lots of programming! Next slides:  Overview of IC design steps  Related courses at U of M  Outline of this course

9. Fall 2006EE 5301 - VLSI Design Automation I I-9 IC Products Processors  CPU, DSP, Controllers Memory chips  RAM, ROM, EEPROM Analog  Mobile communication, audio/video processing Programmable  PLA, FPGA Embedded systems  Used in cars, factories  Network cards System-on-chip (SoC) Images: amazon.com Skip econ

10. Fall 2006EE 5301 - VLSI Design Automation I I-10 IC Product Market Shares Source: Electronic Business

11. Fall 2006EE 5301 - VLSI Design Automation I I-11 The Inverted Pyramid [©Keutzer] Electronic Systems > $1 Trillion Semiconductor > $220 B CAD $3 B

12. Fall 2006EE 5301 - VLSI Design Automation I I-12 Semiconductor Industry Growth Rates Source: http://www.icinsight.com/ (McClean Report)

13. Fall 2006EE 5301 - VLSI Design Automation I I-13 More Demand for EDA Source: http://www.edat.com/edac CAE = Computer Aided Engineering

14. Fall 2006EE 5301 - VLSI Design Automation I I-14 Growth in System Size Source: http://www.edat.com/edac CAGR = Compound Annual Growth Rate

15. Fall 2006EE 5301 - VLSI Design Automation I I-15 Example: Intel Processor Sizes Source: http://www.intel.com/ Intel386 TM DX Processor Intel486 TM DX Processor Pentium® Processor Pentium® Pro & Pentium® II Processors 1.5  1.0  0.8  0.6  0.35  0.25  Silicon Process Technology

16. Fall 2006EE 5301 - VLSI Design Automation I I-16 Moore’s Law 1 10 100 1K 10K 100K 1M 10M 19751980198519901995 Transistors 10x/6 years 8086 68000 68020 80386 80486 68040 8080 4004 Pentium Pro Pentium PPC601 PPC603 MIPS R4000 Microprocessors [©Keutzer]

17. Fall 2006EE 5301 - VLSI Design Automation I I-17 NRTS: Chip Frequencies [©Keutzer] Clock speed GHz 0 1 3 5 7 9 11 1997199920012003200620092012 On-chip, local clock, high performance On-chip, global clock, high performance

18. Fall 2006EE 5301 - VLSI Design Automation I I-18 Increasing Device and Context Complexity Exponential increase in device complexity  Increasing with Moore's law (or faster)! More complex system contexts  System contexts in which devices are deployed (e.g. cellular radio) are increasing in complexity Require exponential increases in design productivity [©Keutzer] We have exponentially more transistors! Complexity

19. Fall 2006EE 5301 - VLSI Design Automation I I-19 Deep Submicron Effects Smaller geometries are causing a wide variety of effects that we have largely ignored in the past:  Cross­coupled capacitances  Signal integrity  Resistance  Inductance [©Keutzer] Design of each transistor is getting more difficult! DSM Effects

20. Fall 2006EE 5301 - VLSI Design Automation I I-20 Heterogeneity on Chip Greater diversity of on­chip elements  Processors  Software  Memory  Analog [©Keutzer] More transistors doing different things! Heterogeneity

21. Fall 2006EE 5301 - VLSI Design Automation I I-21 Stronger Market Pressures Decreasing design window Less tolerance for design revisions [©Keutzer] Time-to-market Exponentially more complex, greater design risk, greater variety, and a smaller design window!

22. Fall 2006EE 5301 - VLSI Design Automation I I-22 A Quadruple­Whammy [©Keutzer] Time-to-market Complexity DSM Effects Heterogeneity

23. Fall 2006EE 5301 - VLSI Design Automation I I-23 Productivity gap Role of EDA: close the productivity gap How Are We Doing? [©Keutzer] Source: SEMATECH Productivity Trans. / Staff. Month 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Tr./S.M Logic transistors per chip (K) 10 100 1,000 10,000 100,000 1,000,000 10,000,000 Logic Tr./Chip 19811985198919931997200120052009 58% / Yr. compound complexity growth rate 21% / Yr. compound productivity growth rate

24. Fall 2006EE 5301 - VLSI Design Automation I I-24 Evolution of the EDA Industry [©Keutzer] Results (design productivity) Effort (EDA tool effort) McKinsey S-Curve Transistor entry – Calma, Computervision, Magic Schematic entry – Daisy, Mentor, Valid Synthesis – Cadence, Synopsys What’s next?

25. Fall 2006EE 5301 - VLSI Design Automation I I-25 IC Design Steps (cont.) Specifications High-level Description Functional Description Behavioral VHDL, C Structural VHDL Figs. [©Sherwani]

26. Fall 2006EE 5301 - VLSI Design Automation I I-26 Packaging Fabri- cation Physical Design Technology Mapping Synthesis IC Design Steps (cont.) Specifications High-level Description Functional Description Placed & Routed Design X=(AB*CD)+ (A+D)+(A(B+C)) Y = (A(B+C)+AC+ D+A(BC+D)) Figs. [©Sherwani] Gate-level Design Gate-level Design Logic Description

27. Fall 2006EE 5301 - VLSI Design Automation I I-27 The Big Picture: IC Design Methods Full Custom ASIC – Standard Cell Design Standard Cell Library Design RTL-Level Design Design Methods Cost / Development Time Quality# Companies involved

28. Fall 2006EE 5301 - VLSI Design Automation I I-28 Optimization: Levels of Abstraction Algorithmic  Encoding data, computation scheduling, balancing delays of components, etc. Gate-level  Reduce fan-out, capacitance  Gate duplication, buffer insertion Layout / Physical-Design  Move cells/gates around to shorten wires on critical paths  Abut rows to share power / ground lines Effectiveness Level of detail

29. Fall 2006EE 5301 - VLSI Design Automation I I-29 Full Custom Design Structural/RTL Description Mem Ctrl Comp. Unit Reg File... Layouts [© Prentice Hall] Component Design Floorplan [©Sherwani] Place & Route A/D PLA I/O comp RAM

30. Fall 2006EE 5301 - VLSI Design Automation I I-30 Full Custom Design Example A/D PLA I/O comp RAM Metal1 Via Metal2 I/O Pad Glue logic (standard cell design) Macro cell design [©Sherwani]

31. Fall 2006EE 5301 - VLSI Design Automation I I-31 ASIC Design Structural/ RTL Description Mem Ctrl Comp. Unit Reg File HDL Programming P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum '0' ); input_nums_read <= '0'; sum_ready <= '0'; P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum '0' ); input_nums_read <= '0'; sum_ready <= '0'; add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o); Mult_i1 <= sum_o(7 downto 0); add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o); Mult_i1 <= sum_o(7 downto 0); Floorplan [©Sherwani] C D A B Cell library D C C B A CC D C D B B C C C

32. Fall 2006EE 5301 - VLSI Design Automation I I-32 ASIC (Standard Cell) Design Example D C C B A CC D C D B B C C C Cell Metal1 Metal2 GNDVDD C D A B Cell library Placement [©Sherwani]

33. Fall 2006EE 5301 - VLSI Design Automation I I-33 Where Is This Course in the Big Picture? VLSI related courses: VLSI CADVLSI DesignOthers EE 4301 Digital Design With Programmable Logic EE 5329 VLSI Digital Signal Processing Systems EE 5333 Analog Integrated Circuit Design EE 5549 Digital Signal Processing Structures for VLSI EE 5323 VLSI Design I EE 5324 VLSI Design II EE 5301 VLSI Design Automation I EE 5302 VLSI Design Automation II

34. Fall 2006EE 5301 - VLSI Design Automation I I-34 Course Outline Basic algorithms and complexity theory  Circuit representations  Classes of problems (P, NP)  Classes of algorithms (dynamic programming, network flow, greedy, linear programming, etc.)  Graph algorithms High-level synthesis  Converting high-level languages to RTL  Scheduling operations  Allocating functional resources (adders, multipliers, registers, etc.)  Register minimization

35. Fall 2006EE 5301 - VLSI Design Automation I I-35 Course Outline (cont.) Partitioning  FM, KL, hMetis algorithms Floorplanning  Slicing, non-slicing floorplans  Simulated annealing floorplanning algorithms Placement / Packing  Force-directed  Simulated annealing  Quadratic placement Global / detailed routing  Maze routing, line-search, Steiner trees, channel routing,

36. Fall 2006EE 5301 - VLSI Design Automation I I-36 To Probe Further... International Technology Roadmap for Semiconductors (ITRS)  http://public.itrs.net/ SEMATECH  http://www.sematech.org/ Textbook  Chapters 1, 2