1 Comparators Discussion D4.3. 2 A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin =

Slides:

Advertisements

Similar presentations

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Advertisements

Arbitrary Waveform Discussion 5.5 Example 34.

Decoders Discussion D9.5 Example 25. Decoders 3-to-8 Decoder decoder38.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all;

Arithmetic Logic Unit (ALU)

Gray Code Converters Discussion D9.1 Example 16.

Shifters Discussion D7.1 Example Bit Shifter.

Divider Discussion D7.3 Example 20.

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Adder Discussion D6.2 Example 17. s i = c i ^ (a i ^ b i ) c i+1 = a i * b i + c i * (a i ^ b i ) Full Adder (Appendix I)

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

Decoders and Encoders Lecture L4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

Logic Design Fundamentals - 3 Discussion D3.2. Logic Design Fundamentals - 3 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Integer Square Root.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

Introduction to VHDL Multiplexers. Introduction to VHDL VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

4-to-1 Multiplexer: case Statement Discussion D2.3 Example 6.

Cascading 1-Bit Comparators Lecture L6.5. A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y.

Logic Design Fundamentals - 2 Lecture L1.2. Logic Design Fundamentals - 2 Basic Gates Basic Combinational Circuits Basic Sequential Circuits.

Introduction to VHDL Multiplexers Discussion D1.1.

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448.

Binary-to-BCD Converter

Arithmetic Logic Unit (ALU) Discussion D4.6. ALU N = negative flag (N=1 if y(n)=0 Z = zero flag (Z = 1 if Y = 0) V = overflow flag C = carry flag.

Binary-to-BCD Converter

4-Bit Binary-to-BCD Converter: case Statement

Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

1 Comparators: Procedures Discussion D9.2 Example 22.

VHDL Examples Subra Ganesan Reference: Professor Haskell’s Notes,

AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs are logic ‘1’.

4-bit Shift Register. 2-bit Register Serial-in-serial-out Shift Register.

1 Part V: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

Data Flow Modeling of Combinational Logic Simple Testbenches

Binary-to-BCD Converter

A.7 Concurrent Assignment Statements Used to assign a value to a signal in an architecture body. Four types of concurrent assignment statements –Simple.

Figure 5.1 Conversion from decimal to binary. Table 5.1 Numbers in different systems.

VHDL for Combinational Circuits. VHDL We Know Simple assignment statements –f

Copyright(c) 1996 W. B. Ligon III1 Getting Started with VHDL VHDL code is composed of a number of entities Entities describe the interface of the component.

ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

EE3A1 Computer Hardware and Digital Design Lecture 2 Introduction to VHDL.

2’s Complement 4-Bit Saturator Discussion D2.8 Lab 2.

4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.

2/10/07DSD,USIT,GGSIPU1 BCD adder KB3B2B1B0CD3D2D1D

CS/EE 3700 : Fundamentals of Digital System Design

BR 8/99 Arithmetic Operations We will review the arithmetic building blocks we have previously used, and look at some new ones. –Addition –incrementer.

Prime Numbers Lecture L6.1 Sieve of Eratosthenes.

Multiplier: Functions Discussion D7.2 Example 19.

EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09.

Registers and Counters Discussion D8.1. Logic Design Fundamentals - 3 Registers Counters Shift Registers.

Combinational logic circuit

Describing Combinational Logic Using Processes

Comparators Discussion DS-3.1.

Combinational Circuits Using VHDL

Logic Design Review – 2 Basic Combinational Circuits

Mano and Kime Sections 7-6 – 7-8

Getting Started with Vivado

A Data Stack CoreGen Discussion 12.1.

Binary-to-BCD Converter

ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic ECE 448 – FPGA and ASIC Design with VHDL.

VHDL (VHSIC Hardware Description Language)

VHDL Structural Architecture

Concurrent vs Sequential

Fibonacci Sequence Lecture L4.1 Lab 3.

Data Flow Description of Combinational-Circuit Building Blocks

Fast, Asynchronous SRAM

Data Flow Description of Combinational-Circuit Building Blocks

Single bit comparator Single bit comparator 4/10/2007 DSD,USIT,GGSIPU

High-Low Guessing Game

4-Input Gates VHDL for Loops

디 지 털 시 스 템 설 계 UP2 Kit를 이용한 카운터 설계

Digital Logic with VHDL

Presentation transcript:

1 Comparators Discussion D4.3

2 A 1-Bit Comparator The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

3 The variable Gout is 1 if x > y or if x = y and Gin = 1. The variable Eout is 1 if x = y and Gin = 0 and Lin = 0. The variable Lout is 1 if x < y or if x = y and Lin = 1.

4 Gout = x * y' + x * Gin + y' * Gin Eout = x' * y' * Gin' * Lin' + x * y * Gin' * Lin' Lout = x' * y + x' * Lin + y * Lin

5 A 4-Bit Comparator

6 Comparators XNOR X Y Z Z = !(X $ Y) Z = X xnor Y Z = Y) Recall that an XNOR gate can be used as an equality detector X Y Z if X = Y then Z <= '1'; else Z <= '0'; end if;

7 4-Bit Equality Comparator A: in STD_LOGIC_VECTOR(3 downto 0); B: in STD_LOGIC_VECTOR(3 downto 0); A_EQ_B: out STD_LOGIC;

8 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity eqdet4 is Port ( A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); A_EQ_B : out std_logic); end eqdet4; architecture Behavioral of eqdet4 is signal C: std_logic_vector(3 downto 0); begin C <= A xnor B; A_EQ_B <= C0 and C1 and C2 and C3; end Behavioral;

9 Comparators comp A(n-1:0) B(n-1:0) A_EQ_B A_GT_B A_LT_B A_UGT_B A_ULT_B A, B signed A, B unsigned Signed: 2's complement signed numbers

10 -- Comparator for unsigned and signed numbers library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity comp is generic(width:positive); port ( A: in STD_LOGIC_VECTOR(width-1 downto 0); B: in STD_LOGIC_VECTOR(width-1 downto 0); A_EQ_B: out STD_LOGIC; A_GT_B: out STD_LOGIC; A_LT_B: out STD_LOGIC; A_ULT_B: out STD_LOGIC; A_UGT_B: out STD_LOGIC ); end comp; comp A(n-1:0) B(n-1:0) A_EQ_B A_GT_B A_LT_B A_UGT_B A_ULT_B

11 architecture comp_arch of comp is begin CMP: process(A,B) variable AVS, BVS: signed(width-1 downto 0); begin for i in 0 to width-1 loop AVS(i) := A(i); BVS(i) := B(i); end loop; A_EQ_B <= '0'; A_GT_B <= '0'; A_LT_B <= '0'; A_ULT_B <= '0'; A_UGT_B <= '0'; if (A = B) then A_EQ_B <= '1'; end if; if (AVS > BVS) then A_GT_B <= '1'; end if; if (AVS < BVS) then A_LT_B <= '1'; end if; if (A > B) then A_UGT_B <= '1'; end if; if (A < B) then A_ULT_B <= '1'; end if; end process CMP; end comp_arch; comp A(n-1:0) B(n-1:0) A_EQ_B A_GT_B A_LT_B A_UGT_B A_ULT_B Note: All outputs must be assigned some value. The last signal assignment in a process is the value assigned

12 4-Bit Comparator