1. Getting Started with Vivado
Tutorial 2

2. Vivado typical design flow

6. The target device choosing (xc7100csg324-1)

7. The next section gives a summary of the options selected throughout the wizard. Verify that the information looks correct and click Finish

8. Workspace

9. 1 2 3

10. 2 1 3

13. open

14. sum <= a xor b ;
carry <= a and b ;

15. save file

16. 1 2

19. 1
right 2

20. open

21. 2 1 architecture bench of HalfAdder_source_beh_tb is
component HalfAdder_source_beh
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end component;
signal a_tb: STD_LOGIC;
signal b_tb: STD_LOGIC;
signal sum_tb: STD_LOGIC;
signal carry_tb: STD_LOGIC;
begin
uut: HalfAdder_source_beh port map ( a => a_tb,
b => b_tb,
sum => sum_tb,
carry => carry_tb );
stimulus: process
a_tb <= '0' ;
b_tb <= '0' ;
wait for 10 ns;
b_tb <= '1' ;
a_tb <= '1' ;
wait;
end process;
end bench; 2 1

23. 1 2

24. 1 2 3

26. 1 2 3

28. open and edit

29. save file

30. 2 1

32. 1 2

33. 1

36. Tutorial Lab. Structure of six different gates a => sw(1),
b => sw(0),
z => ld

37. Tutorial Lab
Schematic after synthesis

38. Schematic – elaborated design

39. library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gates2 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
z : out STD_LOGIC_VECTOR (5 downto 0));
end gates2;
architecture Behavioral of gates2 is
begin
z(5) <= a and b;
z(4) <= a nand b;
z(3) <= a or b;
z(2) <= a nor b;
z(1) <= a xor b;
z(0) <= a xnor b;
end Behavioral;