1. Arithmetic Logic Unit (ALU) Discussion D4.6

2. ALU N = negative flag (N=1 if y(n)=0 Z = zero flag (Z = 1 if Y = 0) V = overflow flag C = carry flag

3. -- An ALU library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity alu is generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); alusel: in STD_LOGIC_VECTOR (2 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0); status: out STD_LOGIC_VECTOR (3 downto 0) ); end alu; alu.vhd

4. architecture alu_arch of alu is begin alu1: process(a,b,alusel) variable AVector: STD_LOGIC_VECTOR (width downto 0); variable BVector: STD_LOGIC_VECTOR (width downto 0); variable yVector: STD_LOGIC_VECTOR (width downto 0); variable Z, C: STD_LOGIC; variable yv: STD_LOGIC_VECTOR (width-1 downto 0); begin AVector := '0' & a; BVector := '0' & b; AVector := '0' & a; status <= "0000"; Z := '0'; C := '0'; alu.vhd (cont.)

5. case alusel is when "000" =>-- a yv := a; when "001" =>-- a + b yVector := AVector + BVector; yv := yVector(width-1 downto 0); C := yVector(width);-- carry flag status(0) <= C;-- carry flag status(1) <= C xor a(width-1) xor b(width-1) xor yv(width-1); -- overflow alu.vhd (cont.)

6. Overflow 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 Overflow = status(1) = C xor C(width-1) = C xor a(width-1) xor b(width-1) xor yv(width-1); C i = A i xor B i xor S i

7. when "010" =>-- a - b yVector := AVector - BVector; yv := yVector(width-1 downto 0); C := yVector(width);-- carry flag status(0) <= C;-- carry flag status(1) <= C xor a(width-1) xor b(width-1) xor yv(width-1); -- overflow when "011" =>-- b - a yVector := BVector - AVector; yv := yVector(width-1 downto 0); C := yVector(width);-- carry flag status(0) <= C;-- carry flag status(1) <= C xor a(width-1) xor b(width-1) xor yv(width-1); -- overflow alu.vhd (cont.)

8. when "100" =>-- not yv := not a; when "101" =>-- a and b yv := a and b; when "110" =>-- a or b yv := a or b; when others =>-- a xor b yv := a xor b; end case; alu.vhd (cont.)

9. Z := '0'; for i in 0 to width-1 loop Z := Z or yv(i);-- Z = '0' if all yv(i) = '0' end loop; status(2) <= not Z;-- zero flag status(3) <= yv(width-1);-- negative flag y <= yv; end process alu1; end alu_arch; alu.vhd (cont.)