CS152 / Kubiatowicz Lec8.1 9/26/01©UCB Fall 2001 CS152 Computer Architecture and Engineering Lecture 8 Designing Single Cycle Control September 26, 2001 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides:

CS152 / Kubiatowicz Lec8.2 9/26/01©UCB Fall 2001 Recap: Summary from last time °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates °Single cycle datapath  CPI=1, Cycle Time = long!

CS152 / Kubiatowicz Lec8.3 9/26/01©UCB Fall 2001 Recap: The MIPS Instruction Formats °All MIPS instructions are 32 bits long. The three instruction formats: R-type I-type J-type °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address bits26 bits oprsrtrdshamtfunct bits 5 bits oprsrt immediate bits16 bits5 bits

CS152 / Kubiatowicz Lec8.4 9/26/01©UCB Fall 2001 Recap: The MIPS-lite Subset (less filling?) °ADD and subtract add rd, rs, rt sub rd, rs, rt °OR Imm: ori rt, rs, imm16 °LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 °BRANCH: beq rs, rt, imm16 oprsrtrdshamtfunct bits 5 bits oprsrtimmediate bits16 bits5 bits

CS152 / Kubiatowicz Lec8.5 9/26/01©UCB Fall 2001 Recap: Overview of the Instruction Fetch Unit °The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC <- PC + 4 -Branch and Jump: PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

CS152 / Kubiatowicz Lec8.6 9/26/01©UCB Fall 2001 Recap: (3a) Add & Subtract °R[rd] <- R[rs] op R[rt] Example: addU rd, rs, rt Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU oprsrtrdshamtfunct bits 5 bits

CS152 / Kubiatowicz Lec8.7 9/26/01©UCB Fall 2001 Recap: Register-Register Timing: One complete cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here

CS152 / Kubiatowicz Lec8.8 9/26/01©UCB Fall 2001 Recap: (3b) Logical Operations with Immediate °R[rt] <- R[rs] op ZeroExt[imm16] ] 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs ZeroExt Mux RtRd RegDst Mux imm16 ALUSrc ALU 11 oprsrtimmediate bits16 bits5 bits rd? immediate bits Rt?

CS152 / Kubiatowicz Lec8.9 9/26/01©UCB Fall 2001 Recap: (3c) Load Operations °R[rt] <- Mem[R[rs] + SignExt[imm16]]Example: lw rt, rs, imm16 11 oprsrtimmediate bits16 bits5 bits rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs RtRd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mu x W_Src ?? Rt?

CS152 / Kubiatowicz Lec8.10 9/26/01©UCB Fall 2001 (3d) Recap: Store Operations °Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 oprsrtimmediate bits16 bits5 bits 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU 32 Mu x W_Src

CS152 / Kubiatowicz Lec8.11 9/26/01©UCB Fall 2001 (3e) Recap: The Branch Instruction °beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal <- R[rs] == R[rt]Calculate the branch condition if (Equal)Calculate the next instruction’s address -PC <- PC ( SignExt(imm16) x 4 ) else -PC <- PC + 4 oprsrtimmediate bits16 bits5 bits

CS152 / Kubiatowicz Lec8.12 9/26/01©UCB Fall 2001 Recap: Datapath for Branch Operations °beq rs, rt, imm16Datapath generates condition (equal) oprsrtimmediate bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Equal? Cond PC Ext Inst Address

CS152 / Kubiatowicz Lec8.13 9/26/01©UCB Fall 2001 Putting it All Together: A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction Imm16RdRtRs = Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory

CS152 / Kubiatowicz Lec8.14 9/26/01©UCB Fall 2001 An Abstract View of the Critical Path °Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: -Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

CS152 / Kubiatowicz Lec8.15 9/26/01©UCB Fall 2001 Questions and Administrative Matters °Monday: selected groups for labs Hopefully everyone is in a group by now…! °Midterm two weeks from Today (Wednesday 10/10): 5:30pm to 8:30pm, TBA (Probably 277 Cory) Make-up quiz? No class on that day (Office hours in my office) Review section previous Sunday? °Midterm reminders: Pencil, calculator, one double-sided 8.5” x 11” page of handwritten notes Sit in every other chair, every other row (odd row & odd seat) °Meet at LaVal’s pizza after the midterm I’ll Buy!

CS152 / Kubiatowicz Lec8.16 9/26/01©UCB Fall 2001 An Abstract View of the Implementation Data Out Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

CS152 / Kubiatowicz Lec8.17 9/26/01©UCB Fall 2001 Recap: A Single Cycle Datapath °Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit °We have everything except ontrol signals (underline) Today’s lecture will show you how to generate the control signals 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel

CS152 / Kubiatowicz Lec8.18 9/26/01©UCB Fall 2001 Recap: Meaning of the Control Signals °nPC_MUX_sel: 0  PC <– PC  PC <– PC SignExt(Im16) || 00 °Later in lecture: higher-level connection between mux and branch cond Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel PC Ext imm16

CS152 / Kubiatowicz Lec8.19 9/26/01©UCB Fall 2001 Recap: Meaning of the Control Signals °ExtOp:“zero”, “sign” °ALUsrc:0  regB; 1  immed °ALUctr:“add”, “sub”, “or” °MemWr:1  write memory °MemtoReg:0  ALU; 1  Mem °RegDst:0  “rt”; 1  “rd” °RegWr:1  write register 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal =

CS152 / Kubiatowicz Lec8.20 9/26/01©UCB Fall 2001 RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct bits 5 bits

CS152 / Kubiatowicz Lec8.21 9/26/01©UCB Fall 2001 Instruction Fetch Unit at the Beginning of Add °Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions PC Ext Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction

CS152 / Kubiatowicz Lec8.22 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Add 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 1 Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] + R[rt] Imm16RdRsRt oprsrtrdshamtfunct nPC_sel= +4

CS152 / Kubiatowicz Lec8.23 9/26/01©UCB Fall 2001 Instruction Fetch Unit at the End of Add °PC <- PC + 4 This is the same for all instructions except: Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_MUX_sel imm16 Instruction 0 1

CS152 / Kubiatowicz Lec8.24 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Or Immediate °R[rt] <- R[rs] or ZeroExt[Imm16] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =

CS152 / Kubiatowicz Lec8.25 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] Imm16RdRsRt oprsrtimmediate nPC_sel= +4

CS152 / Kubiatowicz Lec8.26 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = 0 Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate nPC_sel= +4

CS152 / Kubiatowicz Lec8.27 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Store °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate ALUctr = Clk busW RegWr = 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = Extender Mux imm16 ALUSrc = ExtOp = Mux MemtoReg = Clk Data In WrEn 32 Adr Data Memory 32 MemWr = ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt nPC_sel =

CS152 / Kubiatowicz Lec8.28 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate nPC_sel= +4

CS152 / Kubiatowicz Lec8.29 9/26/01©UCB Fall 2001 The Single Cycle Datapath during Branch 32 ALUctr =Sub Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst = x Extender Mux imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate nPC_sel= “Br”

CS152 / Kubiatowicz Lec8.30 9/26/01©UCB Fall 2001 Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate °What is encoding of nPC_sel? Direct MUX select? Branch / not branch °Let’s choose second option Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction 0 1 Zero nPC_MUX_sel

CS152 / Kubiatowicz Lec8.31 9/26/01©UCB Fall 2001 Step 4: Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Zero Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

CS152 / Kubiatowicz Lec8.32 9/26/01©UCB Fall 2001 A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

CS152 / Kubiatowicz Lec8.33 9/26/01©UCB Fall 2001 A Summary of the Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr x Add x Subtract Or Add x 1 x x 0 x x Subtract x x x x xxx optarget address oprsrtrdshamtfunct oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op Appendix A See We Don’t Care :-)

CS152 / Kubiatowicz Lec8.34 9/26/01©UCB Fall 2001 The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

CS152 / Kubiatowicz Lec8.35 9/26/01©UCB Fall 2001 The Encoding of ALUop °In this exercise, ALUop has to be 2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, and (4) Subtract °To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop xxx

CS152 / Kubiatowicz Lec8.36 9/26/01©UCB Fall 2001 The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct R-type funct Instruction Operation add subtract and or set-on-less-than ALUctr ALU Operation And Or Add Subtract Set-on-less-than P. 286 text: ALUctr ALU

CS152 / Kubiatowicz Lec8.37 9/26/01©UCB Fall 2001 The Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop funct Instruction Op add subtract and or set-on-less-than

CS152 / Kubiatowicz Lec8.38 9/26/01©UCB Fall 2001 The Logic Equation for ALUctr ALUopfunc bit ALUctr 0x1xxxx1 1xx xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func This makes func a don’t care

CS152 / Kubiatowicz Lec8.39 9/26/01©UCB Fall 2001 The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx xx xx10101 °ALUctr = !ALUop & !ALUop + ALUop & !func & !func

CS152 / Kubiatowicz Lec8.40 9/26/01©UCB Fall 2001 The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx xx10101 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

CS152 / Kubiatowicz Lec8.41 9/26/01©UCB Fall 2001 The ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func °ALUctr = !ALUop & !ALUop + ALUop & !func & !func °ALUctr = !ALUop & ALUop + ALUop & !func & func & !func & func + ALUop & func & !func & func & !func

CS152 / Kubiatowicz Lec8.42 9/26/01©UCB Fall 2001 Step 5: Logic for each control signal °nPC_sel <= if (OP == BEQ) then “Br” else “+4” °ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” °ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” °ExtOp <= _____________ °MemWr<= _____________ °MemtoReg<= _____________ °RegWr:<=_____________ °RegDst:<= _____________

CS152 / Kubiatowicz Lec8.43 9/26/01©UCB Fall 2001 Step 5: Logic for each control signal °nPC_sel <= if (OP == BEQ) then “Br” else “+4” °ALUsrc <=if (OP == “Rtype”) then “regB” else “immed” °ALUctr<= if (OP == “Rtype”) then funct elseif (OP == ORi) then “OR” elseif (OP == BEQ) then “sub” else “add” °ExtOp <= if (OP == ORi) then “zero” else “sign” °MemWr<= (OP == Store) °MemtoReg<= (OP == Load) °RegWr:<= if ((OP == Store) || (OP == BEQ)) then 0 else 1 °RegDst:<= if ((OP == Load) || (OP == ORi)) then 0 else 1

CS152 / Kubiatowicz Lec8.44 9/26/01©UCB Fall 2001 The “Truth Table” for the Main Control R-typeorilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPC_sel Jump ExtOp ALUop (Symbolic) x “R-type” Or Add x 1 x x 0 x x Subtract x x x x xxx op ALUop x x x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3RegDst ALUSrc :

CS152 / Kubiatowicz Lec8.45 9/26/01©UCB Fall 2001 The “Truth Table” for RegWrite R-typeorilwswbeqjump RegWrite op °RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite

CS152 / Kubiatowicz Lec8.46 9/26/01©UCB Fall 2001 PLA Implementation of the Main Control RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

CS152 / Kubiatowicz Lec8.47 9/26/01©UCB Fall 2001 A Real MIPS Datapath (CNS T0)

CS152 / Kubiatowicz Lec8.48 9/26/01©UCB Fall 2001 Putting it All Together: A Single Cycle Processor 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb bit Registers Rs Rt Rd RegDst Extender Mux imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction Imm16RdRsRt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr nPC_sel

CS152 / Kubiatowicz Lec8.49 9/26/01©UCB Fall 2001 Recap: An Abstract View of the Critical Path (Load) °Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: -Address valid => Output valid after “access time.” Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address

CS152 / Kubiatowicz Lec8.50 9/26/01©UCB Fall 2001 Worst Case Timing (Load) Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value AddressOld ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time

CS152 / Kubiatowicz Lec8.51 9/26/01©UCB Fall 2001 Drawback of this Single Cycle Processor °Long cycle time: Cycle time must be long enough for the load instruction: PC’s Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew °Cycle time for load is much longer than needed for all other instructions

CS152 / Kubiatowicz Lec8.52 9/26/01©UCB Fall 2001 Preview Next Time: MultiCycle Data Path CPI  1, CycleTime much shorter (~1/5 of time)

CS152 / Kubiatowicz Lec8.53 9/26/01©UCB Fall 2001 °Single cycle datapath => CPI=1, CCT => long °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic °Control is the hard part °MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Summary Control Datapath Memory Processor Input Output

CS152 / Kubiatowicz Lec8.54 9/26/01©UCB Fall 2001 Where to get more information? °Chapter 5.1 to 5.3 of your text book: David Patterson and John Hennessy, “Computer Organization & Design: The Hardware / Software Interface,” Second Edition, Morgan Kaufman Publishers, San Mateo, California, °One of the best PhD thesis on processor design: Manolis Katevenis, “Reduced Instruction Set Computer Architecture for VLSI,” PhD Dissertation, EECS, U C Berkeley, °For a reference on the MIPS architecture: Gerry Kane, “MIPS RISC Architecture,” Prentice Hall.