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Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control.

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Presentation on theme: "Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control."— Presentation transcript:

1 Orange Coast College Business Division Computer Science Department CS 116- Computer Architecture The Processor: Datapath & Control

2 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 2 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 3 Assemble Datapath Meeting Requirements – Build the data path by adding up the components required to execute each instruction – We need to consider: Register transfer requirements Instruction fetch Read operands and execute operation – We are going to consider one instruction format at a time and then combine what we have after each step

3 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 3 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Processor Design Step 3-a Instruction Fetch Unit – Common to all instruction types – Actions taken: Fetch the instruction from Memory: mem[PC] Update program counter: – Sequential Code: PC <- PC + 4 – Branch and Jump: PC <- branch address PC Instruction Memory Read Address 4 Adder

4 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 4 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Consider R-Type instructions R-Format Instructions: – Arithmetic instructions – Logic instructions Main actions: – Read 2 registers – Perform an ALU operation – Write result to destination oprsrtrdshamtfunct 061116212631 6 bits 5 bits

5 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 5 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) R-Type: What do we need? To read data from a register we need – 2-inputs to register file specifying register to be read – 2-outputs from register file will carry the values read Remember output is always available to whatever register# given, therefore no control signal is needed To write data to a register we need – 1-input to register file with register# to write into – 1-data input will carry the data to be written – Write control signal that enables data to be written

6 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 6 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath for R-Format Instructions Main components: Register file RegWri t e Wri t e regis t er Read da t a 1 Read da t a 2 Re ad regis t er 1 Read regis t er 2 Wri t e da t a 5 5 5 ALU Operation ALU resul t ALU Z ero 3

7 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 7 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) R-Type Datapath Datapath for Add & Subtract Instructions R[rd]  R[rs] ± R[rt] – Example: add rd, rs, rt – The register selection lines come from register fields – Control signals are from the control logic after decoding the instruction Opcode + funct

8 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 8 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Now, consider the I-Type Load & Store R[rt]  Mem[R[rs] + SignExt[imm16]] R[rt]  Mem[R[rs] + SignExt[imm16]] – Main actions: Sign-extend offset Add to contents of base register to calculate address Load from or store into the calculated address – We need a sign-extend unit for offset 11 oprsrt/rd?offset 016212631 6 bits16 bits5 bits offset 0 161531 16 bits sign-extended 16-bits

9 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 9 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath for I-Format instructions: Immediate arithmetic operations R[rt]  R[rs] op SignExt[imm16] – Main actions: Sign extend immediate operand Perform operation Store result – We need a “sign-extend” unit for immediate operand 11 oprsrt/rd?offset 016212631 6 bits16 bits5 bits offset 0161531 16 bits sign-extended 16-bits

10 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 10 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath for I-Format instructions: Immediate logical operations R[rt]  R[rs] op ZeroExt[imm16] – Main actions: Zero extend immediate operand Perform operation Store result – We need a “zero-extend” unit for immediate operand 11 oprsrt/rd?immediate 0 16212631 6 bits16 bits5 bits immediate 0 161531 16 bits 0 0 0 0 0 0 0 0

11 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 11 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Load - The Details Use offset in 16 immediate operand bits Value read from memory must be written into register file R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 lw $t1, offset($t2)#$t2 = Base register op rs rt immediate 6 bits 5 bits 5 bits 16 bit 31 26 21 16 0

12 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 12 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Store- The Details Use offset in 16 immediate operand bits Value to be stored read from register file Mem[ R[rs] + SignExt[imm16] ] <- R[rt] Example: sw rt, rs, imm16 sw $t1, offset($t2) #$t2 = Base register op rs rt immediate 6 bits 5 bits 5 bits 16 bit 31 26 21 16 0

13 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 13 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Load & Store- What do we need? Actions: – Register access – Memory address calculation – Read/Write from memory – Write into register (for load) What do we need? – Sign-extend unit – Data memory unit to read/ or write – Both write & read control signals

14 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 14 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Implementation of Load & Store RegWrite Register File W r t e regis t e r Re ad da t a 1 Re ad da t a 2 Read register 1 R e ad r egister 2 Wr te da t a 5 5 5 ALU Operation ALU ALU resu t Zero 3 1 63 2 S i g n e x t end Me m R ea d MemWrite Wr i t e data Rea d da t a A ddre ss Instruction Data Memory

15 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 15 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Combining Datapath components A single datapath can be assembled – From previous datapaths by adding multiplexors One MUX at ALU input to read – Either data bus – Or sign extended word One at the data input to the register file that – Takes the data from ALU – Or from data memory

16 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 16 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Putting it all Together I n s tructi o n 163 2 R egis t e r s W rit e r eg i s t e r R e a d d a ta 1 R e a d d a ta 2 R e a d r eg i s t e r 1 R e a d r eg i s t e r 2 D at a memo ry W ri te d ata R e a d d at a M u x M u x W rit e d at a S i gn ex t e n d ALU r esu lt Z e r o ALU Add r ess Re g Wr ite A L U ope r a t ion 3 MemRead M em W rite ALUSrc Memto R eg

17 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 17 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Combining Datapath components Add in the instruction fetch

18 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 18 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath for Branching (I-Format) Datapath For Branch Instructions (I-Format) beq $t1, $t2, offset Steps: – Compute branch target address – Compare register contents – Determine next instruction based on comparison In MIPS, branches are delayed – Instruction following the branch is always executed Independent of the branch condition – If branch condition is true, backtrack – Helps in speeding up (See pipelining)

19 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 19 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Branching- The details Step1: Compute branch target address – Branch target address = PC + sign-extended offset field – HW needed: sign-extension unit Adder – Notes: Offset could be positive or negative Offset field is “Word offset” – Shift offset left 2 bits (multiply by 4) to get byte offset Branch offset based on instruction following branch – i.e from PC +4

20 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 20 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Branching- The details Step2: Compare register contents – Hardware needed: Register file to get register contents ALU to perform comparison – By subtraction

21 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 21 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Branching- The details Step3: Determine next instruction – Depends on the result of comparison – If condition is true: Branch is taken – If condition is false Branch is not taken – Hardware needed: ALU: – Zero signal from ALU if the result is zero indicating the condition is true

22 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 22 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Branching- The details Step 4: Modify instruction fetch datapath – If branch is taken PC  Branch target address – If branch not taken PC  PC +4 – Hardware needed Adder

23 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 23 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) The Branching Datapath RegWrite Read Reg1 5 5 ALU Control ALU Zero 3 16 32 Add Sum Shift left 2 Branch target To branch control logic Instruction PC +4 from instruction datapath Read Reg2 Write Reg Write data Register File Read Data1 Read Data2 Sign extend

24 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 24 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Finally, the J-type j target Unconditional jump – Requires no comparison Target is “Word target” – Target needs shifting 2 bits to the left – Original target 26 bits – Target after shifting 28 bits Target need to be loaded into PC – The lower 28 bits of PC are replaced with target Hardware needed: – Concatenating “00” unit 2target 6 bits26 bits

25 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 25 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) The Combined Datapath 1 clock cycle for each operation – Load/store, ALU operations, Branches

26 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 26 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Critical Path for Load Total time needed = PC’s change time + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew

27 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 27 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Assemble Control Logic Control Unit – Analyze implementation of each instruction to determine setting of control points Instruction Inst Memory Address Control Imm16RdRsRt OpFun ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal nPC_sel RegWr DATA PATH

28 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 28 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) What control signals do we need? Register selection: – Rs, Rt, Rd and Imed16 hardwired into datapath Operation selection: – nPC_sel: 0 => PC PC <– PC + 4 + SignExt(Im16) || 00 Extension 16-bit control – ExtOp:“zero”, “sign” ALU data source – Register or immediate address – ALUsrc:0 => regB; 1 => immed

29 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 29 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) What control signals do we need? ALU Operation selection (control) – ALUctr: “add”, “sub”, “or” Memory Write: – MemWr MemtoReg: – 1 => Mem RegDst: – 0 => “rt”; 1 => “rd” RegWr: – write dest register

30 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 30 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Control Signals for each instruction inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc=RegB, ALUctrl=“add”, RegDst=rd, RegWr, nPC_sel=“+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc=RegB, ALUctr=“sub”, RegDst=rd, RegWr, nPC_sel=“+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc=Im, Extop=“Z”, ALUctr=“or”, RegDst=rt, RegWr, nPC_sel=“+4”

31 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 31 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Control Signals for each instruction inst Register Transfer LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4 ALUsrc=Im, Extop=“Sn”, ALUctr=“add”, MemWr, nPC_sel=“+4” BEQif (R[rs]== R[rt]) then PC<– PC+sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = EQUAL, ALUctr = “sub”

32 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 32 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Assemble each signal nPC_sel <= if (OP==BEQ) then EQUAL else 0 ALUsrc <= if (OP==“000000”) then “regB” else “immed” ALUctr <= if (OP==“000000”) then functelseif (OP==ORi) then “OR” elseif (OP==BEQ) then “SUB” else “ADD”

33 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 33 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Assemble each signal ExtOp <= if (OP == ORi) then “zero” else “sign” MemWr <= (OP == Store) MemtoReg <= (OP == Load) RegWr: <= if ((OP== Store) || (OP==BEQ)) then 0 else 1 RegDst: <= if ((OP==Load) || (OP==ORi)) then 0 else 1

34 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 34 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Datapath with Control Unit

35 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 35 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Summary 5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

36 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 36 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Summary MIPS makes it easier – Instructions are all the same size – Source registers are always in same place in the instruction – Immediate operands are the same size & in the same location – Operations are always on either register contents or immediate operands Single cycle datapath => CPI=1

37 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 37 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) The Control Unit Functions: – Select operations to be performed (ALU, read/write, etc.) – Control data flow (multiplexor inputs) Major components: – ALU control Operation based on instruction type and function code – Other controls Input: – Information comes from the 32 bits of the instruction Output: – Control signals Control Unit Instruction code Control Signals

38 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 38 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) Quick review: MIPS Instruction Formats optarget address 0 2631 6 bits26 bits oprsrtrdshamtfunct 0 6 11 16 21 2631 6 bits 5 bits rsoprt immediate 0 16 21 2631 6 bits16 bits5 bits R-type I-type J-type

39 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 39 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) ALU Control ALU has 3 control inputs – Allows 8-combinations Only 5 combinations are used. – The rest could be used as don’t-care in minimization 000 AND 001OR 010add 110subtract 111set-on-less-than

40 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 40 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) ALU Control Remember: – ALU is needed for all instruction categories lw/sw(I-Format): Compute memory address Arithmetic/logic(R-Format): Arithmetic / logic operation Branch(beq)(I-Format): Subtract registers – We need to find ALU control signals from the information in the instruction 1111010100x2a0SLL 1101000100x220SUB 0101000000x200ADD 0011001010x250OR 0001001000x240AND ALU Control Funct- Binary Funct- field0x Op-fieldInstruction

41 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 41 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) ALU Control ALU performs one of 5 instructions based on instruction class ALUOp: – A 2-bit input control used with the “funct” field Determines 3-bit combination to control the ALU ALUOp Control 6-bit “funct feld” 2-bit “ALUOp” input 00 Add(for load & store) 01 Subtract (for beq) 10 Depends on code in funct field 3-bit “ALU operation” 000 and 001 or 010 add 110 sub 111 slt

42 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 42 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) How ALU control bits are set (ALUOp = 00 or 01 ) – Depend on “op” field & not on “funct” field (ALUOp code = 10 ) – Depend on “funct” field to set the ALU control input 1 2 1 2

43 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 43 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) ALU Control Multiple level of decoding is used 1. The main control unit generates the ALUOp bits 2. ALUOp bits are used as input to ALU control 3. ALU control generates the actual signal to ALU unit Why use multiple levels? – Reduce size of main control unit – Increase speed of control unit

44 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 44 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) ALU Control: Truth Table 8-input lines, 3 output lines – Actual table size should be 2 8 = (256) – Only relevant combinations are listed Details in (Appendix C2, p. C4) F5 & F4 are always don’t cares – F3-F0 only are considered

45 OCC - CS/CIS CS116-Ch00-Orientation 1998 Morgan Kaufmann Publishers ( Augmented & Modified by M.Malaty) 45 OCC-CS 116 Fall 2003 1998 Morgan Kaufmann Publishers (Augmented & Modified by M.Malaty and M. Beers) ALU Control: Logic Circuit Details in Appendix C2, p. C4 Based on “funct” code & ALUOp Operation2 ALU operation (Control signals) F 3 F2 F1 F 0 F ( 5 – 0 ) ALUOp0 ALUOp ALU Control Circuit Diagram 3 2 5 ALUOp1 Operation1 Operation0

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