EI209 Chapter 4B.1Haojin Zhu, SJTU 2015 EI 209 Computer Organization Fall 2015 Chapter 4B: The Processor, Control and Multi-cycle Datapath [Adapted from.

EI209 Chapter 4B.1Haojin Zhu, SJTU 2015 EI 209 Computer Organization Fall 2015 Chapter 4B: The Processor, Control and Multi-cycle Datapath [Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, © 2012, MK]

EI209 Chapter 4B.2Haojin Zhu, SJTU 2015 Recap: A Summary of Control Signals inst Register Transfer ADDR[rd] <– R[rs] + R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4” SUBR[rd] <– R[rs] – R[rt];PC <– PC + 4 ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4” ORiR[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4 ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4” LOADR[rt] <– MEM[ R[rs] + sign_ext(Imm16)];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4” STOREMEM[ R[rs] + sign_ext(Imm16)] <– R[rs];PC <– PC + 4 ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4” BEQif ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4 nPC_sel = “Br”, ALUctr = “sub”

EI209 Chapter 4B.3Haojin Zhu, SJTU 2015 Step 5: Assemble Control logic ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Decoder Op Fun RegWr

EI209 Chapter 4B.4Haojin Zhu, SJTU 2015 addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtr 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtr x x x 0 0 0 1 x xxx optarget address oprsrtrdshamtfunc 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op 00 0000 00 1101 10 001110 101100 010000 0010 10 000010 0010 We Don’t Care :-) A Summary of the Control Signals

EI209 Chapter 4B.5Haojin Zhu, SJTU 2015 func Main Control op 6 ALU Control ( Local ) N=? 6 ALUop ALUctr 3 ALU Two levels of decoding: Main Control and ALU Control ALUctr is determined by ALUop and func, while other control signals are determined by op 。 How many bits will N need? R 、 I-ori 、 I-lw/sw 、 I-beq 、 J The Concept of Local Decoding 3, why?

EI209 Chapter 4B.6Haojin Zhu, SJTU 2015 R-typeorilwswbeqjump ALUop ( Symbolic )“ R-type ” OrAdd Subtr xxx ALUop 1 xx0 100 00 0x1 xxx Main Control op 6 ALU Control ( Local ) func N 6 ALUop ALUctr 3 000000 rsrtrdshamtfunc 061116212631 R-type func Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 100 101 010 Add Subtract And Or Subtract ALUctr ALU Encoding ALUop as follows Could ALUop use just 2 bits ？ Yes ！ Since jump is X ， we could use 2 bits ： R:11, I-ori:10, I-beq:01, I-lw/sw:00, J-xx R-Type is1xx ， could identify R-instruction by using 1 bit ！ The Decoding of the “func” Field

EI209 Chapter 4B.7Haojin Zhu, SJTU 2015 R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtr ALUop 1 000 100 00 0 x1 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than The Truth Table for ALUctr Non-R-type Instructions determined by ALUop R-type Instructions determined by funct

EI209 Chapter 4B.8Haojin Zhu, SJTU 2015 The Logic Equation for ALUctr  ALUctr = !ALUop & ALUop + ALUop & !func & func & !func ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 This makes func a don’t care Choose the rows with ALUctr[0]=1

EI209 Chapter 4B.9Haojin Zhu, SJTU 2015 The Logic Equation for ALUctr ALUopfunc bit 010xxxx1 ALUctr 1xx01001 1xx01011  ALUctr = !ALUop & ALUop & ! ALUop + ALUop & !func & func & !func Choose the rows with ALUctr[1]=1

EI209 Chapter 4B.10Haojin Zhu, SJTU 2015 The Logic Equation for ALUctr ALUopfunc bit ALUctr 010xxxx1 1xx01011  ALUctr = !ALUop & ALUop & !ALUop + ALUop & !func & func & !func & func Choose the rows with ALUctr[2]=1

EI209 Chapter 4B.11Haojin Zhu, SJTU 2015 Summery of Control Logic of Local Control ALU Control ( Local ) func 3 6 ALUop ALUctr 3  ALUctr = !ALUop & ALUop + ALUop & !func & func & !func  ALUctr = !ALUop & ALUop & !ALUop + ALUop & !func & func & !func  ALUctr = !ALUop & ALUop & !ALUop + ALUop & !func & func & !func & func

EI209 Chapter 4B.12Haojin Zhu, SJTU 2015 R-typeori lw swbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) 1 0 0 1 0 0 0 x “ R-type ” 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtr x x x 0 0 0 1 x xxx op00 000000 1101 10 0011 10 101100 010000 0010 ALUop 10 0 0 0 x x1 0 0 x x x0 0 0 1 x Main Control op 6 ALU Control ( Local ) func 3 6 ALUop ALUctr 3 RegDst ALUSrc : Input of main control Output of Main Control The “Truth Table” for the Main Control

EI209 Chapter 4B.13Haojin Zhu, SJTU 2015 R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010  RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite Decoder The “Truth Table” for RegWrite

EI209 Chapter 4B.14Haojin Zhu, SJTU 2015 op.... op.. op.. op.. op.. R-typeorilwswbeqjump RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop Decoder The “Truth Table” for RegWrite

EI209 Chapter 4B.15Haojin Zhu, SJTU 2015 The Complete Single Cycle Data Path with Control 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Ext Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 3232 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction Jump Branch 0 1 0 1 01 Imm16RdRsRt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr

EI209 Chapter 4B.16Haojin Zhu, SJTU 2015 Time Delay for LW: Critical Path Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWrOld ValueNew Value Delay through Control Logic busA Register File Access Time Old ValueNew Value busB ALU Delay Old ValueNew Value Old ValueNew Value Old Value ExtOpOld ValueNew Value ALUSrcOld ValueNew Value MemtoRegOld ValueNew Value AddressOld ValueNew Value busWOld ValueNew Delay through Extender & Mux Register Write Occurs Data Memory Access Time PC+4 PC+4 PC

EI209 Chapter 4B.17Haojin Zhu, SJTU 2015 Performance of Single-Cycle Machine  Assume that the operation times for the major functional units in this implementation are the following l Memory units: 200 picoseconds l ALU and adders: 100 ps l Register file (read or write): 50 ps Assuming that the multiplexors, control unit, PC accesses, sign extension unit, and wires have no delay, which of the following implementations would be faster and by how much? 1. An implementation in which every instruction operates in 1 clock cycle of a fixed length. 2. An implementation where every instruction executes in 1 clock cycle using a variable-length clock. To compare the performance, assume the following instruction mix: 25% loads, 10% stores, 45% ALU instructions, 15 % branches, and 5% jumps.

EI209 Chapter 4B.18Haojin Zhu, SJTU 2015 What’s wrong with our CPI=1 processor? PCInst Memory mux ALUData Mem mux PCReg FileInst Memory mux ALU mux PCInst Memory mux ALUData Mem PCInst Memorycmp mux Reg File Arithmetic & Logical Load Store Branch Critical Path setup

EI209 Chapter 4B.19Haojin Zhu, SJTU 2015 200501000350 200 Instr.I MemReg RdALU OpD MemReg WrTotal R- type load store beq jump 2005010020050600 20050100200550 Instruction Critical Paths 20050100050400  Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires, setup and hold times) except: l Instruction and Data Memory (200 ps) l ALU and adders (100 ps) l Register File access (reads or writes) (50 ps)

EI209 Chapter 4B.20Haojin Zhu, SJTU 2015 Comparison of clock cycles for two implementation 2. An implementation where every instruction executes in 1 clock cycle using a variable-length clock. 1.An implementation in which every instruction operates in 1 clock cycle of a fixed length. CPU clock cycle=600*25%+550*10%+400*45%+350*15%+200*5% =447.5 ps CPU clock cycle=600 ps (longest instruction)

EI209 Chapter 4B.21Haojin Zhu, SJTU 2015 Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction l especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  Is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

EI209 Chapter 4B.22Haojin Zhu, SJTU 2015 Multicycle Implementation Overview  Each instruction step takes 1 clock cycle l Therefore, an instruction takes more than 1 clock cycle to complete  Not every instruction takes the same number of clock cycles to complete  Multicycle implementations allow l faster clock rates l different instructions to take a different number of clock cycles l functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result -only need one memory -only need one ALU/adder

EI209 Chapter 4B.23Haojin Zhu, SJTU 2015 The Multicycle Datapath – A High Level View Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout  Registers have to be added after every major functional unit to hold the output value until it is used in a subsequent clock cycle

EI209 Chapter 4B.24Haojin Zhu, SJTU 2015 Clocking the Multicycle Datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout System Clock MemWriteRegWrite clock cycle

EI209 Chapter 4B.25Haojin Zhu, SJTU 2015  Break up the instructions into steps where each step takes a clock cycle while trying to l balance the amount of work to be done in each step l use only one major functional unit per clock cycle  At the end of a clock cycle l Store values needed in a later clock cycle by the current instruction in a state element (internal register not visible to the programmer) IR – Instruction Register MDR – Memory Data Register A and B – Register File read data registers ALUout – ALU output register -All (except IR) hold data only between a pair of adjacent clock cycles (so they don’t need a write control signal) l Data used by subsequent instructions are stored in programmer visible state elements (i.e., Register File, PC, or Memory) Our Multicycle Approach

EI209 Chapter 4B.26Haojin Zhu, SJTU 2015 The Complete Multicycle Data with Control Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.27Haojin Zhu, SJTU 2015  Reading from or writing to any of the internal registers, Register File, or the PC occurs (quickly) at the beginning (for read) or the end of a clock cycle (for write)  Reading from the Register File takes ~50% of a clock cycle since it has additional control and access overhead (but reading can be done in parallel with decode)  Had to add multiplexors in front of several of the functional unit input ports (e.g., Memory, ALU) because they are now shared by different clock cycles and/or do multiple jobs  All operations occurring in one clock cycle occur in parallel l This limits us to one ALU operation, one Memory access, and one Register File access per clock cycle Our Multicycle Approach, con’t

EI209 Chapter 4B.28Haojin Zhu, SJTU 2015 1. Instruction Fetch 2. Instruction Decode and Register Fetch 3. R-type Instruction Execution, Memory Read/Write Address Computation, Branch Completion, or Jump Completion 4. Memory Read Access, Memory Write Completion or R-type Instruction Completion 5. Memory Read Completion (Write Back) INSTRUCTIONS TAKE FROM 3 - 5 CYCLES! Five Instruction Steps

EI209 Chapter 4B.29Haojin Zhu, SJTU 2015 RTL for Instructions  Common Steps: l Instr fetch IR = Memory[PC]; l PC Updating PC = PC + 4;  Decode and Register reading l A = Reg[IR[25-21]]; B = Reg[IR[20-16]];  Instruction Dependent operation

EI209 Chapter 4B.30Haojin Zhu, SJTU 2015 RTL for Instructions  Instruction Dependent operation Execute ALUOut = A op B; ALUOut = A + sign- extend (IR[15-0]); if (A==B) PC = ALUOut; ALUOut = PC +(sign- extend(IR[15- 0])<< 2); PC = PC[31-28] ||(IR[25-0] << 2); Memory access Reg[IR[15 -11]] = ALUOut; MDR = Memory[ALUOu t]; or Memory[ALUOu t] = B; Write-back Reg[IR[20- 16]] = MDR;

EI209 Chapter 4B.31Haojin Zhu, SJTU 2015 Group Discussion 1  Four-six members form a group and discuss the following questions related to multi-cycle datapath?  1. What are the task for each step?(balance the load of each step to minimize the number of clock cycles)  Recommend one member to present your results?

EI209 Chapter 4B.32Haojin Zhu, SJTU 2015 Multi-cycle datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.33Haojin Zhu, SJTU 2015 RTL Summary StepR-typeMem RefBranchJump Instr fetch IR = Memory[PC]; PC = PC + 4; Decode A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); Execute ALUOut = A op B; ALUOut = A + sign-extend (IR[15-0]); if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25- 0] << 2); Memory access Reg[IR[15 -11]] = ALUOut; MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] = MDR;

EI209 Chapter 4B.34Haojin Zhu, SJTU 2015 Group Discussion 2  Four-six members form a group and discuss the following questions related to multi-cycle datapath?  1. What are data paths and control signals for each step of each instruction?  Recommend one member to present your results?

EI209 Chapter 4B.35Haojin Zhu, SJTU 2015 Multi-cycle datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.36Haojin Zhu, SJTU 2015  Use PC to get instruction from the memory and put it in the Instruction Register  Increment the PC by 4 and put the result back in the PC  Can be described succinctly using the RTL "Register- Transfer Language“ IR = Memory[PC]; PC = PC + 4; Step 1: Instruction Fetch Can we figure out the values of the control signals? What is the advantage of updating the PC now?

EI209 Chapter 4B.37Haojin Zhu, SJTU 2015 Datapath Activity During Instruction Fetch Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

EI209 Chapter 4B.38Haojin Zhu, SJTU 2015 Fetch Control Signals Settings Start Instr Fetch

EI209 Chapter 4B.39Haojin Zhu, SJTU 2015 Fetch Control Signals Settings Start Instr Fetch IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

EI209 Chapter 4B.40Haojin Zhu, SJTU 2015  Don’t know what the instruction is yet, so can only l Read registers rs and rt in case we need them l Compute the branch address in case the instruction is a branch  The RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2);  Note we aren't setting any control lines based on the instruction (since we don’t know what it is (the control logic is busy "decoding" the op code bits)) Step 2: Instruction Decode and Register Fetch

EI209 Chapter 4B.41Haojin Zhu, SJTU 2015 Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.42Haojin Zhu, SJTU 2015 Datapath Activity During Instruction Decode Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

EI209 Chapter 4B.43Haojin Zhu, SJTU 2015 Decode Control Signals Settings Start Instr Fetch Decode Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

EI209 Chapter 4B.44Haojin Zhu, SJTU 2015 Decode Control Signals Settings Start Instr Fetch Decode ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X

EI209 Chapter 4B.45Haojin Zhu, SJTU 2015  ALU is performing one of four functions, based on instruction type  Memory reference ( lw and sw ): ALUOut = A + sign-extend(IR[15-0]);  R-type: ALUOut = A op B;  Branch: if (A==B) PC = ALUOut;  Jump: PC = PC[31-28] || (IR[25-0] << 2); Step 3 (instruction dependent)

EI209 Chapter 4B.46Haojin Zhu, SJTU 2015 Datapath Activity During lw & sw Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.47Haojin Zhu, SJTU 2015 Datapath Activity During lw & sw Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 00

EI209 Chapter 4B.48Haojin Zhu, SJTU 2015 Datapath Activity During R-type Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.49Haojin Zhu, SJTU 2015 Datapath Activity During R-type Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 10

EI209 Chapter 4B.50Haojin Zhu, SJTU 2015 Datapath Activity During beq Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.51Haojin Zhu, SJTU 2015 Datapath Activity During beq Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 01

EI209 Chapter 4B.52Haojin Zhu, SJTU 2015 Datapath Activity During j Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.53Haojin Zhu, SJTU 2015 Datapath Activity During j Execute Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.54Haojin Zhu, SJTU 2015 Execute Control Signals Settings Start Instr Fetch Decode Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

EI209 Chapter 4B.55Haojin Zhu, SJTU 2015 Execute Control Signals Settings Start Instr Fetch Decode (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite Execute Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite

EI209 Chapter 4B.56Haojin Zhu, SJTU 2015  Memory reference: MDR = Memory[ALUOut]; -- lw or Memory[ALUOut] = B; -- sw  R-type instruction completion Reg[IR[15-11]] = ALUOut;  Remember, the register write actually takes place at the end of the cycle on the clock edge Step 4 (also instruction dependent)

EI209 Chapter 4B.57Haojin Zhu, SJTU 2015 Datapath Activity During lw Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.58Haojin Zhu, SJTU 2015 Datapath Activity During lw Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.59Haojin Zhu, SJTU 2015 Datapath Activity During sw Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.60Haojin Zhu, SJTU 2015 Datapath Activity During sw Memory Access Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.61Haojin Zhu, SJTU 2015 Datapath Activity During R-type Completion Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.62Haojin Zhu, SJTU 2015 Datapath Activity During R-type Completion Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.63Haojin Zhu, SJTU 2015 Memory Access Control Signals Settings Start Instr Fetch Decode Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite

EI209 Chapter 4B.64Haojin Zhu, SJTU 2015 Memory Access Control Signals Settings Start Instr Fetch Decode Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite

EI209 Chapter 4B.65Haojin Zhu, SJTU 2015  All we have left is the write back into the register file the data just read from memory for lw instruction Reg[IR[20-16]]= MDR; What about all the other instructions? Step 5: Memory Read Completion (Write Back)

EI209 Chapter 4B.66Haojin Zhu, SJTU 2015 Datapath Activity During lw Write Back Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.67Haojin Zhu, SJTU 2015 Datapath Activity During lw Write Back Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

EI209 Chapter 4B.68Haojin Zhu, SJTU 2015 Write Back Control Signals Settings Start Instr Fetch Decode Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 MemRead IorD=1 PCWriteCond=0

EI209 Chapter 4B.69Haojin Zhu, SJTU 2015 Write Back Control Signals Settings Start Instr Fetch Decode Write Back Memory Access Execute (Op = R-type) (Op = beq) (Op = lw or sw) (Op = j) (Op = lw) (Op = sw) RegDst=0 RegWrite MemtoReg=1 PCWriteCond=0 Unless otherwise assigned PCWrite,IRWrite, MemWrite,RegWrite=0 others=X IorD=0 MemRead;IRWrite ALUSrcA=0 ALUsrcB=01 PCSource,ALUOp=00 PCWrite ALUSrcA=0 ALUSrcB=11 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=10 ALUOp=00 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=10 PCWriteCond=0 ALUSrcA=1 ALUSrcB=00 ALUOp=01 PCSource=01 PCWriteCond PCSource=10 PCWrite MemRead IorD=1 PCWriteCond=0 MemWrite IorD=1 PCWriteCond=0 RegDst=1 RegWrite MemtoReg=0 PCWriteCond=0

EI209 Chapter 4B.70Haojin Zhu, SJTU 2015 RTL Summary StepR-typeMem RefBranchJump Instr fetch IR = Memory[PC]; PC = PC + 4; Decode A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC +(sign-extend(IR[15-0])<< 2); Execute ALUOut = A op B; ALUOut = A + sign-extend (IR[15-0]); if (A==B) PC = ALUOut; PC = PC[31-28] ||(IR[25- 0] << 2); Memory access Reg[IR[15 -11]] = ALUOut; MDR = Memory[ALUOut]; or Memory[ALUOut] = B; Write- back Reg[IR[20-16]] = MDR;

EI209 Chapter 4B.71Haojin Zhu, SJTU 2015 Example Using the following instruction mix, what is the CPI, assuming that each state in the multicycle CPU requires 1 clock cycle? Load25% store10% branches11% jumps2% ALU52%

EI209 Chapter 4B.72Haojin Zhu, SJTU 2015 Answer: Loads:5 Stores:4 ALU: 4 Branches:3 Jumps:3 CPI=0.25*5+0.10*4+0.52*4+0.11*3+0.02*3=4.12

EI209 Chapter 4B.1Haojin Zhu, SJTU 2015 EI 209 Computer Organization Fall 2015 Chapter 4B: The Processor, Control and Multi-cycle Datapath [Adapted from.

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EI209 Chapter 4B.1Haojin Zhu, SJTU 2015 EI 209 Computer Organization Fall 2015 Chapter 4B: The Processor, Control and Multi-cycle Datapath [Adapted from.

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Presentation on theme: "EI209 Chapter 4B.1Haojin Zhu, SJTU 2015 EI 209 Computer Organization Fall 2015 Chapter 4B: The Processor, Control and Multi-cycle Datapath [Adapted from."— Presentation transcript:

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