Logic Design Fundamentals - 3 Discussion D3.2

Logic Design Fundamentals - 3 Basic Gates Basic Combinational Circuits Basic Sequential Circuits

Logic Design Fundamentals - 3 Latches Flip-Flops Registers Counters Shift Registers

R-S Latch R S Q Q is set to 1 when S is asserted, and remains unchanged when S is disasserted. Q is reset to 0 when R is asserted, and remains unchanged when R is disasserted. Assertions can be active HIGH or active LOW

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '1' and R = '0' then Q <= '1'; elsif S = '0' and R = '1' then Q <= '0'; end if; end process; end rslatch; R-S Latch R S Q Active HIGH

R-S Latch -- Active High

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rslatch is port( R : in STD_LOGIC; S : in STD_LOGIC; Q : out STD_LOGIC ); end rslatch; architecture rslatch of rslatch is begin process(R,S) begin if S = '0' and R = '1' then Q <= '1'; elsif S = '1' and R = '0' then Q <= '0'; end if; end process; end rslatch; R-S Latch R S Q Active LOW

R-S Latch -- Active Low

D Latch D EN Q Q follows D when EN is high, and remains unchanged when EN is low..

library IEEE; use IEEE.STD_LOGIC_1164.all; entity dlatch is port( D : in STD_LOGIC; EN : in STD_LOGIC; Q : out STD_LOGIC ); end dlatch; architecture dlatch of dlatch is begin process(D,EN) begin if EN = '1' then Q <= D; end if; end process; end dlatch; D Latch D EN Q

D Latch

D Flip-Flop X 0 Q 0 !Q 0 D clk Q !Q D gets latched to Q on the rising edge of the clock. Positive edge triggered if rising_edge(clk) then Q <= D; end if; Behavior clk D Q !Q

library IEEE; use IEEE.STD_LOGIC_1164.all; entity dflipflop is port( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC ); end dflipflop; architecture dflipflop of dflipflop is signal QS: STD_LOGIC; begin process(D,clk) begin if rising_edge(clk) then QS <= D; end if; end process; Q <= QS; NotQ <= not QS; end dflipflop; clk D Q !Q

D Flip-Flop

library IEEE; use IEEE.STD_LOGIC_1164.all; entity dflipflop is port( D : in STD_LOGIC; clk : in STD_LOGIC; Q : out STD_LOGIC; NotQ : out STD_LOGIC ); end dflipflop; architecture dflipflop of dflipflop is signal QS: STD_LOGIC; begin process(D,clk) begin if clk'event and clk = '1' then QS <= D; end if; end process; Q <= QS; NotQ <= not QS; end dflipflop; clk D Q !Q

D Flip-Flop

A 1-Bit Register if rising_edge(CLK) then if LOAD = ‘1’ then Q0 <= INP0; end if; Behavior

A 4-Bit Register

library IEEE; use IEEE.std_logic_1164.all; entity reg is generic(width: positive); port ( d: in STD_LOGIC_VECTOR (width-1 downto 0); load: in STD_LOGIC; clr: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (width-1 downto 0) ); end reg; A Generic Register

architecture reg_arch of reg is begin process(clk, clr) begin if clr = '1' then for i in width-1 downto 0 loop q(i) <= '0'; end loop; elsif (clk'event and clk = '1') then if load = '1' then q <= d; end if; end process; end reg_arch; Infers a flip-flop for all outputs (q)

3-Bit Counter if clr = '1' then count <= "000"; elsif rising_edge(clk) then count <= count + 1; end if; Q <= count; Behavior signal count: STD_LOGIC_VECTOR (2 downto 0); count3 clr clk q(2 downto 0)

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity count3 is port( clk : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC_VECTOR(2 downto 0) ); end count3; architecture count3 of count3 is signal count: STD_LOGIC_VECTOR(2 downto 0); begin process(clr,clk) begin if clr = '1' then count <= "000"; elsif clk'event and clk = '1' then count <= count + 1; end if; end process; q <= count; end count3; count3.vhd Asynchronous clear Need signal because q can not be read Signal count increments on rising edge of clk

count3 Simulation

signal clk, cclk: std_logic; signal clkdiv: std_logic_vector(23 downto 0); begin -- Divide the master clock (50Mhz) down to a lower frequency. process (mclk) begin if mclk = '1' and mclk'event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0);-- mclk/2 = 25 MHz cclk <= clkdiv(17);-- mclk/2 18 = 190 Hz Clock Divider mclk = 50 MHz master clock

4-Bit Shift Register s(3) s(2) s(1) s(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1); end loop; s(3) := data_in; end if; Behavior

library IEEE; use IEEE.STD_LOGIC_1164.all; entity shift4 is port( data_in : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end shift4; architecture shift4 of shift4 is begin process(clr,clk) variable s: STD_LOGIC_VECTOR(3 downto 0); begin if clr = '1' then s := "0000"; elsif clk'event and clk = '1' then for i in 0 to 2 loop s(i) := s(i+1); end loop; s(3) := data_in; end if; Q <= s; end process; end shift4; shift4.vhd

shift4 simulation

Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0); end if; Behavior s(3) s(2) s(1) s(0) Note: Must use signals here

library IEEE; use IEEE.STD_LOGIC_1164.all; entity ring4 is port( clk : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end ring4; architecture ring4 of ring4 is signal s: STD_LOGIC_VECTOR(3 downto 0); begin process(reset,clk) begin if reset = '1' then s <= "0001"; elsif clk'event and clk = '1' then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0); end if; end process; Q <= s; end ring4; ring4.vhd Note: Must use signals here

ring4 simulation

A Random Number Generator if rising_edge(CLK) then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0) xor s(3); end if; Behavior s(3) s(2) s(1) s(0)

Q3 Q2 Q1 Q C E F B Q3 Q2 Q1 Q A D

library IEEE; use IEEE.STD_LOGIC_1164.all; entity rand4 is port( clk : in STD_LOGIC; reset : in STD_LOGIC; Q : out STD_LOGIC_VECTOR(3 downto 0) ); end rand4 ; architecture rand4 of rand4 is signal s: STD_LOGIC_VECTOR(3 downto 0); begin process(reset,clk) begin if reset = '1' then s <= "0001"; elsif clk'event and clk = '1' then for i in 0 to 2 loop s(i) <= s(i+1); end loop; s(3) <= s(0) xor s(3); end if; end process; Q <= s; end rand4; rand4.vhd

rand4 simulation

clock_pulse

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity clock_pulse is port ( inp, cclk, clr: in std_logic; outp: out std_logic ); end clock_pulse; clock_pulse

architecture clock_pulse_arch of clock_pulse is signal delay1, delay2, delay3: std_logic; begin process(cclk, clr) begin if clr = '1' then delay1 <= '0'; delay2 <= '0'; delay3 <= '0'; elsif cclk'event and cclk='1' then delay1 <= inp; delay2 <= delay1; delay3 <= delay2; end if; end process; outp <= delay1 and delay2 and (not delay3); end clock_pulse_arch; clock_pulse