Random Number Generator Dimtriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager- Thiago Hersan

Status Finished C implementation Architecture Verilog Datapath design In Process…  Simulation  Gate-Level Design  Preliminary Floorplan Unfinished Schematic Layout Extraction, LVS, post-layout simulation

Design Decisions Alpha 8 2 sets of 32 x 32 SRAM One dual bus SRAM Main adder unit chosen

Pipeline – Version Stages 5 clock cycles (ticks) per stage. Not all registers update on the same tick value Assumptions –32-bit addition in two ticks –SRAM read in half a tick

Random Numbers  With original seed of all 1’s: –AA38AF8A8F A122CBF C16055A026C FD9254F E6713B5D9A144E7F7385D61A5B443B 0824C6B5AE5BB18535C0A09FE D1DDA642BB0763 2F26A872E048E203327C1F55BC126A8A2B814D5F1E23CB 71565F DAF0A1E41C9E89DC7DCEF91F E25B7F55B1419A49129EF5 –81B1CC28F282CD1C EADE85E278B3DE0519C F4C24399F7014A E2AF4974C45AC92BED C8D3B07FB4E7F60D81C86C A600BE0152B4E6D4 DF2A93B5075B5B1AA8CF406F5EAE D9DAF745C A98A FFE94E5C224890BCA1E3CF2 8F6C56A247C2912A8BBCD79AF

Project Main Blocks

Main DataPath

Stage 1 Receive I, I_prev ) M1=M[i+32] | A1=(A >13) ) X=M[i]| A=A1+M NOTE: Y get's updated at start of this tick 2) M3=M[X]| A=A1+M1| C1=(X==i-1) ) Y1=A+ (C1) ? Y : M ) Y1 = A + M

Stage 1

Stage 2 Receive B, Y1, X, I ) Y=B+Y1| YL=B[13:0]+Y1[13:0] ) Y=B+Y1| M4=M[Y[13:8]] | C2=(I==Y[13:8]) ) B = X+(C2) ? Y : M ) B = X+(C2) ? Y : M4| M[i]=Y ) R[i] = B

Stage 2

Other optimizations Memory and registers updated at different edges of clock. One special adder