Specification Test Minimization for Given Defect Level Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA 15 th IEEE Latin-American Test Workshop Fortaleza, Brazil March 13, 2014

Problem Statement Given a set of complete specification-based tests for an analog or RF circuit, and An acceptable defect level (DL), Find the smallest set of tests that should be used. 3/13/2014LATW 2014: Spec. Test Minimization2

Motivation 3/13/2014LATW 2014: Spec. Test Minimization3 International Technology Roadmap for Semiconductors (ITRS)

What is Defect Level? 3/13/2014LATW 2014: Spec. Test Minimization4 Tested good Tested bad All fabricated chips Good chip Bad chip Defect level: DL = 2/21 Yield loss: YL = 1/30 True yield: Y = 20/30

Definitions and Assumption Specification S i is tested by test T i. Probability of testing S j by T i Is p ij. Assume that specification tests have zero defect level: p 11 = p 22 = ● ● ● = 1.0 This is perhaps the reason why the users and manufacturers of VLSI have more confidence in specification tests than in alternate tests. This assumption can be relaxed in the future work. 3/13/2014LATW 2014: Spec. Test Minimization5

A Bipartite Graph 3/13/2014LATW 2014: Spec. Test Minimization6 T2T2 T3T3 T1T1 T4T4 S1S1 S2S2 S3S3 S4S4 p 11 p 22 p 33 p 44 p 34 p 42 p 12 p 21 p 13 Tests Specifications

An Integer Linear Program (ILP) Consider k specifications and k tests. Define k integer [0,1] variables {x i } for tests {T i }: Discard T i if x i = 0, else retain T i Define objective function: k minimize ∑ x i i=1 Next, need linear constraints to stay within given defect level. 3/13/2014LATW 2014: Spec. Test Minimization7

Defect Level: A Faulty Device Passes Defect level is probability of a faulty device passing all tests, i.e., Prob{All tests pass | device is faulty} For given defect level (dl), this conditional probability should not exceed dl, i.e., k 1 – ∏ P(S j ) ≤ dl j=1 Where, P(S j ) = Probability of testing specification S j k = 1 – ∏ (1 – p ij ) x i i=1 3/13/2014LATW 2014: Spec. Test Minimization8

Giving Equal Weight per Specification Assume that each specification weighs equally in determining defect level, P(S 1 ) = P(S 2 ) = ● ● ● = P(S k ) or 1 – [P(S j )] k ≤ dl or(1 – dl) 1/k ≤ P(S j ), j = 1, 2, ● ● ●, k k or (1 – dl) 1/k ≤ P(S j ) = 1 – ∏ (1 – p ij ) x i i=1 j = 1, 2, ● ● ●, k 3/13/2014LATW 2014: Spec. Test Minimization9

Linear Constraints We derive k linear constraint relations for variables x i and constant dl: k (1 – dl) 1/k ≤ 1 – ∏ (1 – p ij ) x i, j = 1, 2, ● ● ●, k i=1 Therefore, k ∑ x i ln (1 – p ij ) ≤ ln[1 – (1 – dl) 1/k ], i=1 j = 1, 2, ● ● ●, k 3/13/2014LATW 2014: Spec. Test Minimization10

Operational Amplifier: TI LM741 3/13/2014LATW 2014: Spec. Test Minimization11

LM741 Specifications Test SpecificationValues Unit DescriptionMin.Nom.Max. T1T1 DC gain50200V/mV T2T2 Slew rate0.30.5V/μs T3T3 3-dB bandwidth0.41.5MHz T4T4 Input referred offset voltage ± 10 ± 15mV T5T5 Power supply rejection ratio8696dB T6T6 Common mode rejection ratio8095dB T7T7 Input bias current3080nA 3/13/2014LATW 2014: Spec. Test Minimization12

Monte Carlo Simulation Simulate sample circuits for tests T 1 through T 7 using spice. 5,000 circuit samples generated: 5% random deviation around nominal value of each components (12 resistors and 1 capacitor) 10% random deviation in DC gain of each BJT 3/13/201413LATW 2014: Spec. Test Minimization

Compute probabilities p ij X = circuits failing T i Y = circuits failing T j Z = circuits failing both T i and T j p ij = Prob{Test T j fails | spec S i is faulty} = Z/Y Example: 45 circuits had spec. S 1 failure, detected by T 1 81 circuits had spec. S 2 failure, detected by T 2 17 circuits had both failures p 12 = 17/81 = 0.21, p 21 = 17/45 = 0.38, p 11 = p 22 = 1.0 3/13/201414LATW 2014: Spec. Test Minimization

Spice Simulation of 5,000 Samples p 12 =17/81 = /13/2014LATW 2014: Spec. Test Minimization15 p 21 = 17/45 = 0.38 Samples failing T 1

Probabilities p ij for LM741 3/13/2014LATW 2014: Spec. Test Minimization16 p ij T1T1 T2T2 T3T3 T4T4 T5T5 T6T6 T7T7 S1S S2S S3S S4S S5S S6S S7S

ILP Define x i  [0,1], such that x i = 0  discard T i. Objective function: 7 minimize ∑ x i i=1 Subject to: 7 ∑ x i ln (1 – p ij ) ≤ ln[1 – (1 – dl) 1/7 ], i=1 j = 1, 2, ● ● ●, 7 where dl = defect level 3/13/2014LATW 2014: Spec. Test Minimization17

Test Minimization 3/13/2014LATW 2014: Spec. Test Minimization18 DL PPM ILP solution Tests selected Test size reduction x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x % % % 1, % 10, %

Conclusion ILP provides an effective tradeoff between test cost (test time) and quality (defect level). Test time may further reduce if shorter tests are favored in the cost function. The assumption of equal weight for each specification can be removed by adding weight to critical specifications. Defect introduction in Monte Carlo samples need careful examination. Diagnostic tests may need to preserve diagnostic resolution rather than defect level. Applications to alternate test could be a useful extension. 3/13/2014LATW 2014: Spec. Test Minimization19