1. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design1 ELEC 7770: Advanced VLSI Design Spring 2014 Model-Based and Alternate Tests Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14

2. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design2 Analog Test  Analog circuits  Analog circuit test methods  Specification-based testing  Direct measurement  DSP-based testing  Fault model based testing  Alternate Test  Summary  References

3. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design3 Analog Circuits  Operational amplifier (analog)  Programmable gain amplifier (mixed-signal)  Filters, active and passive (analog)  Comparator (mixed-signal)  Voltage regulator (analog or mixed-signal)  Analog mixer (analog)  Analog switches (analog)  Analog to digital converter (mixed-signal)  Digital to analog converter (mixed- signal)  Phase locked loop (PLL) (mixed-signal)

4. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design4 Test Parameters  DC  Continuity  Leakage current  Reference voltage  Impedance  Gain  Power supply – sensitivity, common mode rejection  AC  Gain – frequency and phase response  Distortion – harmonic, intermodulation, nonlinearity, crosstalk  Noise – SNR, noise figure

5. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design5 Filter Analog Test (Traditional) Analog device under test (DUT) ~ DC ETC. DC RMS PEAK ETC. StimulusResponse

6. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design6 DSP-Based Mixed-Signal Test Mixed-signal device under test (DUT) A/DRAM D/A Send memory Receive memory Analog Digital Synchronization Digital signal processor (DSP) Vectors SynthesizerDigitizer

7. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design7 Waveform Synthesizer © 1987 IEEE

8. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design8 Waveform Digitizer © 1987 IEEE

9. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design9 Circuit Specification Key Performance Specifications: TLC7524C 8-bit Multiplying Digital-to-Analog Converter Resolution8 Bits Linearity error½ LSB Max Power dissipation at V DD = 5 V5 mW Max Settling time100 ns Max Propagation delay time80 ns Max

10. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design10 Voltage Mode Operation Data Latches VOVO CS WR RRR R 2R DB7 (MSB) DB6DB5DB0 (LSB) GND R FB OUT1 OUT2 Data Inputs VIVI REF V O = V I (D/256) VDD = 5 V OUT1 = 2.5 V OUT2 = GND 01 000111

11. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design11 Operational/Timing Spec. ParameterTest conditionsFor VDD = 5 V Linearity error ±0.5 LSB Gain error Measured using the internal feedback resistor. Normal full scale range (FSR) = Vref – 1 LSB ±2.5 LSB Settling time to ½ LSBOUT1 load = 100 Ω, Cext = 13 pF, etc. 100 ns Prop. Delay, digital input to 90% final output current 80 ns CS WR DB0-DB7 t su (CS) ≥ 40 ns t h (CS) ≥ 0 ns t w (WR) ≥ 40 ns t su (D) ≥ 25 ns t h (D) ≥ 10 ns

12. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design12 Operating Range Spec. Supply voltage, V DD -0.3 V to 16.5 V Digital input voltage range-0.3 V to V DD +0.3 V Reference voltage, V ref ±25 V Peak digital input current10μA Operating temperature-25ºC to 85ºC Storage temperature-65ºC to 150ºC Case temperature for 10 s260ºC

13. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design13 Test Plan: Hardware Setup DACOUT 2.5 V +Full-scale code R LOAD 1 kΩ + V out - Vref D7-D0 VM +-+-

14. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design14 Test Program Pseudocode dac_full_scale_voltage() { set VI1 = 2.5 V; /* Set the DAC voltage reference to 2.5 V */ start digital pattern = “dac_full_scale”; /* Set DAC output to +full scale (2.5 V) */ connect meter: DAC_OUT /* Connect voltmeter to DAC output */ fsout = read_meter(), /* Read voltage level at DAC_OUT pin */ test fsout; /* Compare the DAC full scale output to data sheet limit */ }

15. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design15 Analog Fault Models A 1 First stage gainR 2 / R 1 A 2 High-pass filter gainR 3 and C 1 f C1 High-pass filter cutoff frequency C 1 and R 3 A 3 Low-pass AC voltage gainR 4, R 5 and C 2 A 4 Low-pass DC voltage gainR 4 and R 5 f C2 Low-pass filter cutoff frequencyC 2 and R 5 Op Amp High-pass filter Low-pass filter amplifier

16. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design16 Bipartite Graph of Circuit Minimum set of parameters to be observed

17. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design17 Method of ATPG Using Sensitivities  Compute analog circuit sensitivities  Construct analog circuit bipartite graph  From graph, find which O/P parameters (performances) to measure to guarantee maximal coverage of parametric faults  Determine which O/P parameters are most sensitive to which component faults  Evaluate test quality, add test points to complete the analog fault coverage N. B. Hamida and B. Kaminska, “Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling,” Proc. ITC-1993.

18. Sensitivity  Sensitivity of a circuit parameter y to variation in a component value x is, S(x,y) = (∆y/y)/(∆x/x)where ∆x is small  For our example, a parameter y can be gain or cutoff frequency and components are resistors and capacitors. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design18

19. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design19 Sensitivity  Simulate the circuit with all components at nominal values.  Determine sensitivity of one parameter- component pair at a time:  Find the minimum component value deviation, positive or negative, such that a measurable performance parameter deviation is produced.  Repeat for all parameter-component pairs.

20. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design20 Sensitivity Matrix of Circuit -0.91 0 R 1 100000R2100000R2 0 0.58 -0.91 0 C 1 0 0.38 -0.89 0 R 3 0 -0.96 -0.97 0 R 4 0 0.48 -0.97 -0.88 R 5 0 -0.48 0 -0.91 C 2 A 1 A 2 fc 1 A 3 A 4 fc 2 Numbers in orange show highest sensitivity for a component.

21. Tolerance  Tolerance of a parameter y with respect to variation in a component value x is, Range A ≤ ∆x/x ≤ B such that y remains within specification. All other components are assumed to have nominal values. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design21

22. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design22 Tolerance Box: Single-Parameter Variation A1A2A4A1A2A4 5% ≤ ≤ 15.98% 5% ≤ ≤ 14.10% 5% ≤ ≤ 20.27% 5% ≤ ≤ 11.60% 5% ≤ ≤ 15.00% ΔR1R1ΔR2R2ΔR3R3ΔC1C1ΔR4R4ΔR5R5ΔR1R1ΔR2R2ΔR3R3ΔC1C1ΔR4R4ΔR5R5 fC1fC2A3fC1fC2A3 5% ≤≤ 14.81% 5% ≤≤ 15.20% 5% ≤≤ 14.65% 5% ≤≤ 13.96% 5% ≤≤ 15.00% 5% ≤≤ 35.00% ΔR3R3ΔC1C1ΔR5R5ΔC2C2ΔR4R4ΔR5R5ΔC2C2ΔR3R3ΔC1C1ΔR5R5ΔC2C2ΔR4R4ΔR5R5ΔC2C2

23. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design23 Weighted Bipartite Graph Five tests provide most sensitive measurement of all components

24. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design24 IEEE 1149.4 Standard Analog Test Bus (ATB)

25. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design25 Digital/Analog Interfaces At any time, only 1 analog pin can be stimulated and only 1 analog pin can be read

26. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design26 Summary  DSP-based tester has:  Waveform synthesizer  Waveform digitizer  High frequency clock with dividers for synchronization  Analog test methods  Specification-based functional testing  Model-based analog testing  Analog test bus allows static analog tests of mixed-signal devices  Boundary scan is a prerequisite

27. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design27 References on Analog Test  A. Afshar, Principles of Semiconductor Network Testing, Boston: Butterworth-Heinemann, 1995.  M. Burns and G. Roberts, Introduction to Mixed-Signal IC Test and Measurement, New York: Oxford University Press, 2000.  M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2000.  R. W. Liu, editor, Testing and Diagnosis of Analog Circuits and Systems, New York: Van Nostrand Reinhold, 1991.  M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, Los Alamitos, California: IEEE Computer Society Press, 1987.  A. Osseiran, Analog and Mixed-Signal Boundary Scan, Boston: Springer, 1999.  T. Ozawa, editor, Analog Methods for Computer-Aided Circuit Analysis and Diagnosis, New York: Marcel Dekker, 1988.  B. Vinnakota, editor, Analog and Mixed-Signal Test, Upper Saddle River, New Jersey: Prentice-Hall PTR, 1998.

28. Setting Thresholds in Model-Based Test  In model-based test, component values are determined.  Preset “thresholds” for component variation classify the device under test as good or faulty.  How do we determine the “thresholds”. For example,  Circuit is good if R1’ ≤ R1 ≤ R1’’ Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design28

29. An Operational Amplifier Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design29 Gain = V2/V1 = R2/R1 V1 V2 R1 R2 +_+_

30. Pessimism in Model-Based Test Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design30 0 R1 R2 Only good devices accepted Yield loss Slope = G 0

31. Reducing Yield Loss Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design31 0R1 R2 Faulty devices accepted Reduced yield loss 0 Slope = G

32. Yield Loss and Defect Level  Yield loss: Amount of yield reduction because some good devices fail non-functional tests.  Defect level (DL): Fraction of faulty devices among those that pass non-functional tests.  Example: 1,0000 devices are fabricated. 7,000 are good. True yield, y = 0.7. Test passes 6,900 good and 150 bad devices. Then,  Yield loss = (7,000 – 6,900)/10,000 = 0.01 or 1%  DL = 150/(6,900+150) = 0.02128 or 2.128% or 21,280 DPM (defective parts per million) Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design32

33. Yield Loss and Defect Level Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design33 All fabricated devices Good devices Yield loss Defect level Devices passing test

34. Component Variation (Statistical) Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design34 Component (R or C) value Mean Component (R or C) value Mean UniformGaussian

35. Monte Carlo Simulation  Consider operational amplifier example.  R1 and R2 are random variables with given (uniform or Gaussian) probability density functions with  Mean = nominal value  Standard deviation based on manufacturing data  Generate large number of samples for R1 and R2  Simulate each sample using spice  Determine gain for each sample  For each set of tolerance limits, determine yield loss and defect level. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design35

36. Monte Carlo Simulation Data Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design36 R1 0 R2 0 Slope = G

37. Setting Test Limits Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design37 0R1 R2 Minimize yield loss Minimize defect level 0 Slope = G

38. Alternate Test  Besides components (e.g., R1 and R2 for operational amplifier) easily measurable parameters used for testing.  An example is the supply current IDD of the operational amplifier.  A simple test is to measure IDD(0) for 0V input.  Monte Carlo simulation is then used to set the limits on IDD(0).  Large number of sample circuits with component variations are simulated to determine thresholds for IDD(0).  Additional measurements can improve test. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design38

39. Alternate Test: Setting Thresholds Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design39 0 IDD(0) Gain Minimize yield loss Minimize defect level 0 Within spec. gain FailPassFail

40. Zero Defect Level Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design40 0 IDD(0) Gain Yield loss increased Zero defect level 0 Within spec. gain FailPassFail

41. Zero Yield Loss Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design41 0 IDD(0) Gain Zero yield loss Increased defect level 0 Within spec. gain FailPassFail

42. References  P. N. Variyam, S. Cherubal and A. Chatterjee, “Prediction of Analog Performance Parameters Using Fast Transient Testing,” IEEE Trans. Computer-Aided Design, vol. 21, no. 3, pp. 349- 361, March 2002.  H.-G. Stratigopoulos and Y. Makris, “Error Moderation in Low-Cost Machine-Learning- Based Analog/RF Testing,” IEEE Trans. Computer-Aided Design, vol. 27, no. 2, pp. 339- 351, February 2008. Spring 2014, Apr 7...ELEC 7770: Advanced VLSI Design42