1. Testing in the Fourth Dimension
Vishwani D. Agrawal
Bell Labs, Murray Hill, NJ USA
The 9th Asian Test Symposium
Taipei, December 4, 2000
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2. Present and Future*
Feature size (micron)
Transistors/sq. cm M M
Pin count
Clock rate (MHz)
Power (Watts)
* SIA Roadmap, IEEE Spectrum, July 1999
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3. Cost of Testing in 2000AD
GHz, analog instruments,1,024 digital pins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/yr
Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
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4. Challenges of Testing
High-speed tests for transition faults or critical paths are useless unless tests are applied by the ATE at the rated clock speed
Too expensive to replace current ATE with high-speed ATE
Non-availability of high-speed ATE and lack of compatibility among ATE manufacturers
Speed gap between VLSI speed and ATE speed may always exist
Noise problems (coupling, mismatch, etc.) in high-speed ATE to DUT interface
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5. A Test Problem Many VLSI devices and systems today are
designed to operate at clock rates that
exceed the production test capability.
There is need for test methods using the
available ATE, that will insure that the
tested parts work at the rated clock speed.
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6. Methods of Timing Test Indirect Methods Ring oscillator
Create long non-functional paths for testing
Direct Methods
ATE pin multiplexing
Reduced voltage testing
Variable (slow-fast) clock testing
Built-in controllable delay
At-speed BIST
High-speed clock with slow ATE I/O
Ref: Krstic and Cheng, Delay Fault Testing for VLSI Circuits, Kluwer, 1998
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7. Reduced Voltage Test
If a circuit passes a slow-speed test at a reduced VDD, then it is expected to work at a higher clock rate with normal VDD (Wagner and McCluskey, ICCAD-85; Hao and McCluskey, ITC-93)
Path delay, T(Vdd) = aT0 (1 + kb) + (1 - a)T0
Vdd = supply voltage during test
T0 = path delay at rated supply VDD
a = delay fraction due to gates on path
b = (VDD - Vdd)/VDD
k = technology-dependent constant
Low voltage critical paths may be different
Reduced voltage operation is noise-sensitive
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8. A Delay Test (V1,V2) V1 V2 Inputs Comb. logic Outputs Output strobe
Transient
region
Output
strobe
V1 V2
Inputs
Comb.
logic
Outputs
time
Clock period
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9. Slow-Clock Test Input Combinational Output latches circuit latches
test clock
Output
test clock
Rated
period
Test
period
Input
test clock
Output
test clock
Output
latched V1 V2
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10. Slow-Clock Test Problems
General non-scan circuits: Low path coverage, ATPG too complex
Scan circuits: Vector-pair (V1,V2) restricted by either scan-shift or functional mode, low path coverage
Enhanced-scan circuits: High combinational path testability, hold-latch overhead, long test time
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11. Inserting Delay for Test
Control
Controlled
delay d
Combinational logic
maxdelay < T - d FF FF CK
Test clock period, T
F(rated) -- F(test)
d =
F(rated) . F(test)
Example: F(rated) = 500MHz, F(test) = 50MHz, d = 18ns
Reference: Agrawal and Chakraborty, ITC-95
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12. A Controlled Delay Circuit
Data in
Data out
Control T CK
Control
Rated clock
period d
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13. Delay Insertion Pros and Cons
Functional paths tested
Direct test for logic and timing by slow ATE
Test circuitry tested for logic and timing
Area overhead
Delay overhead
Design of timing critical test circuitry and control signals
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14. At-Speed BIST Test-points added for random-pattern testability
Scan structure used for test application
High-speed clock and control signals either generated on circuit under test or supplied by ATE
Boundary-scan used to test system-on-a-chip and core-based systems
Activation of long non-functional paths can cause problem
Ref: Nadeau-Dostie, Design for At-Speed Test, Diagnosis and Measurement, Kluwer, 2000
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15. An At-Speed BIST Example
BSM2 (Boundary-scan master) chip, Higgins and Srinivasan, VTS-00
Lucent 0.35micron CMOS process
65MHz 3.3V, 19k gates, 1.4k FFs
Test: memory BIST, logic BIST, scan
453k logic BIST and scan vectors
96% stuck-at fault coverage
165k paths tested (total 400M paths)
Longest tested path - 58 gates (74 max.)
BIST fails good parts if run above 40MHz
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16. At-Speed Clock/Slow I/O
Krstic et al., VTS-99; Agrawal and Parodi, Test Synthesis Workshop-99
Apply inputs and sample outputs with a test clock N times slower than rated clock; N is test speed reduction factor
Apply rated clock to flip-flops
Delay output sample strobe by interval s = rated-clock period = (test clock period)/N
Repeat test application successively increasing sample strobe delay to 2s, 3s, Ns
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17. At-Speed Clock/Slow I/O CoveragePI PO
FFs
Speed reduction
factor, N = 2
Input vectors applied
Test clock period 1 2 1 2 1 2 1
time
Rated clock
period, s
Output sample strobe
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18. At-Speed Clock/Slow I/O Simulation Result
5,000 Random vectors 40 30 5
PDF coverage (%) 20 10 1 2 3 4
Speed reduction factor, N
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19. Conclusion At-speed test may be unavoidable in the future
ATE speeds will lag behind the state of the art VLSI chips and systems
There is need for delay test methods that can work with ATE limitations
New DFT methods should allow delay testing in a similar manner as scan does for DC tests:
Test path, transition and stuck-at faults
Test DFT hardware for logic and timing
Reasonable DFT overhead (less than 10%)
Study of timing in new technologies should lead to new models of delay faults, as well as to validation of existing models
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