1. ELEC 7770: Advanced VLSI Design Spring 2016 Analog and RF Test Strategies
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

2. Types of Analog RF Tests
Specification based test: Test to verify specified behavior.
Model based test: Test for modeled faults in circuit components (resistors, capacitors, transistors). A typical fault is an out of range component.
Alternate test: Testing focuses on easily measurable parameters, whose out of range values indicate specification failures.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

3. ELEC 7770: Advanced VLSI Design (Agrawal)
References
A. Afshar, Principles of Semiconductor Network Testing, Boston: Butterworth-Heinemann, 1995.
M. Burns and G. Roberts, Introduction to Mixed-Signal IC Test and Measurement, New York: Oxford University Press, 2000.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Springer, 2000.
R. W. Liu, editor, Testing and Diagnosis of Analog Circuits and Systems, New York: Van Nostrand Reinhold, 1991.
M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, Los Alamitos, California: IEEE Computer Society Press, 1987.
A. Osseiran, Analog and Mixed-Signal Boundary Scan, Boston: Springer, 1999.
T. Ozawa, editor, Analog Methods for Computer-Aided Circuit Analysis and Diagnosis, New York: Marcel Dekker, 1988.
B. Vinnakota, editor, Analog and Mixed-Signal Test, Upper Saddle River, New Jersey: Prentice-Hall PTR, 1998.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

4. Specification Test Cost Reduction
Given a set of complete specification-based tests for an analog or RF circuit, and
An acceptable defect level (DL),
Find the smallest set of tests that should be used.
Reference:
S. Sindia and V. D. Agrawal, “Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests,” J. Electronic Testing: Theory and Applications (JETTA), vol. 31, no. 5, pp , October 2015.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

5. ELEC 7770: Advanced VLSI Design (Agrawal)
Motivation
International Technology Roadmap for Semiconductors (ITRS)
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

6. ELEC 7770: Advanced VLSI Design (Agrawal)
What is Defect Level?
Good chip
Bad chip
Tested good
Defect level:
DL = 2/21
Yield loss:
YL = 1/30
Tested bad
True yield:
Y = 20/30
All fabricated chips
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

7. Definitions and Assumption
Specification Si is tested by test Ti.
Probability of testing Sj by Ti Is pij.
Assume that specification tests have zero defect level:
p11 = p22 = ● ● ● = 1.0
This is perhaps the reason why the users and manufacturers of VLSI have more confidence in specification tests than in alternate tests.
This assumption can be relaxed in the future work.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

8. ELEC 7770: Advanced VLSI Design (Agrawal)
A Bipartite Graph
Tests T1 T2 T3 T4
p12
p33
p13
p11
p22
p42
p44
p21
p34 S1 S2 S3 S4
Specifications
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

9. An Integer Linear Program (ILP)
Consider k specifications and k tests.
Define k integer [0,1] variables {xi} for tests {Ti }:
Discard Ti if xi = 0, else retain Ti
Define objective function: k
minimize ∑ xi
i=1
Next, need linear constraints to stay within given defect level.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

10. Defect Level: A Faulty Device Passes
Defect level is probability of a faulty device passing all tests, i.e.,
Prob{All tests pass | device is faulty}
For given defect level (dl), this conditional probability should not exceed dl, i.e., k
1 – ∏ P(Sj) ≤ dl
j=1
Where, P(Sj) = Probability of testing specification Sj
= 1 – ∏ (1 – pij)xi
i=1
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

11. Giving Equal Weight per Specification
Assume that each specification weighs equally in determining defect level,
P(S1) = P(S2) = ● ● ● = P(Sk)
or – [P(Sj)]k ≤ dl
or (1 – dl)1/k ≤ P(Sj), j = 1, 2, ● ● ● , k k
or (1 – dl)1/k ≤ P(Sj) = 1 – ∏ (1 – pij)xi
i=1
j = 1, 2, ● ● ● , k
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

12. ELEC 7770: Advanced VLSI Design (Agrawal)
Linear Constraints
We derive k linear constraint relations for variables xi and constant dl: k
(1 – dl)1/k ≤ 1 – ∏ (1 – pij)xi, j = 1, 2, ● ● ● , k
i=1
Therefore,
∑ xi ln(1 – pij) ≤ ln[1 – (1 – dl)1/k],
i= j = 1, 2, ● ● ● , k
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

13. Operational Amplifier: TI LM741
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

14. ELEC 7770: Advanced VLSI Design (Agrawal)
LM741 Specifications
Test
Specification
Values
Unit
Description
Min.
Nom.
Max. T1
DC gain 50
200
V/mV T2
Slew rate
0.3
0.5
V/μs T3
3-dB bandwidth
0.4
1.5
MHz T4
Input referred offset voltage
±10
±15 mV T5
Power supply rejection ratio 86 96 dB T6
Common mode rejection ratio 80 95 T7
Input bias current 30 nA
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

15. Monte Carlo Simulation
Simulate sample circuits for tests T1 through T7 using spice.
5,000 circuit samples generated:
5% random deviation around nominal value of each components (12 resistors and 1 capacitor)
10% random deviation in DC gain of each BJT
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

16. Compute probabilities pij
X = circuits failing Ti
Y = circuits failing Tj
Z = circuits failing both Ti and Tj
pij = Prob{Test Tj fails | spec Si is faulty} = Z/Y
Example:
45 circuits had spec. S1 failure, detected by T1
81 circuits had spec. S2 failure, detected by T2
17 circuits had both S1 and S2 failures
p12 = 17/81 = 0.21, p21 = 17/45 = 0.38, p11 = p22 = 1.0
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

17. Spice Simulation of 5,000 Samples
Samples failing
p12 = 17/81
= 0.21
p21 = 17/45
= 0.38
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

18. Probabilities pij for LM741
1.00
0.38
0.78
0.51
0.76
0.93
0.98 S2
0.21
0.75
0.20
0.27
0.35 S3
0.56
0.97
0.19 S4
0.92
0.64
0.48
0.84 S5
0.59
0.57 S6
0.80
0.54
0.62
0.37
0.42
0.87 S7
0.61
0.31
0.33
0.43
0.63
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

19. ELEC 7770: Advanced VLSI Design (Agrawal)
ILP
Define xi  [0,1], such that xi = 0  discard Ti.
Objective function: 7
minimize ∑ xi
i=1
Subject to:
∑ xi ln(1 – pij) ≤ ln[1 – (1 – dl)1/7],
i= j = 1, 2, ● ● ● , 7
where dl = defect level
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

20. ELEC 7770: Advanced VLSI Design (Agrawal)
Test Minimization DL
PPM
ILP solution
Tests selected
Test size reduction x1 x2 x3 x4 x5 x6 x7 1 7 0% 6
14%
100
1,000 5
29%
10,000 4
43%
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

21. About Test Optimization
ILP provides an effective tradeoff between test cost (test time) and quality (defect level).
Test time may further reduce if shorter tests are favored in the cost function.
The assumption of equal weight for each specification can be removed by adding weight to critical specifications.
Defect introduction in Monte Carlo samples need careful examination.
Diagnostic tests may need to preserve diagnostic resolution rather than defect level.
Applications to alternate test could be a useful extension.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

22. ELEC 7770: Advanced VLSI Design (Agrawal)
Model-Based Test
In model-based test, component values are measured.
Specifications must be highly sensitive to variations in selected component values.
N. B. Hamida and B. Kaminska, “Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling,” Proc. ITC-1993.
Preset “thresholds” for component variation classify the device under test as good or faulty.
Determine “thresholds”,
Circuit is good if R1’ ≤ R1 ≤ R1’’
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

23. An Operational Amplifier+ _
Gain = V2/V1 = R2/R1 V1 V2
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

24. Pessimism in Model-Based Test
Slope = G
Yield
loss R2
Only good
devices
accepted R1
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

25. ELEC 7770: Advanced VLSI Design (Agrawal)
Reducing Yield Loss
Slope = G
Reduced
yield loss R2
Faulty
devices
accepted R1
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

26. Yield Loss and Defect Level
Yield loss: Amount of yield reduction because some good devices fail non-functional tests.
Defect level (DL): Fraction of faulty devices among those that pass non-functional tests.
Example: 1,0000 devices are fabricated. 7,000 are good. True yield, y = 0.7. Test passes 6,900 good and 150 bad devices. Then,
Yield loss = (7,000 – 6,900)/10,000 = 0.01 or 1%
DL = 150/(6, ) = or 2.128% or 21,280 DPM (defective parts per million)
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

27. Yield Loss and Defect Level
All fabricated devices
Devices
passing
test
Good
devices
Defect
level
Yield
loss
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

28. Component Variation (Statistical)
Uniform
Gaussian
Mean
Mean
Component (R or C) value
Component (R or C) value
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

29. Monte Carlo Simulation
Consider operational amplifier example.
R1 and R2 are random variables with given (uniform or Gaussian) probability density functions with
Mean = nominal value
Standard deviation based on manufacturing data
Generate large number of samples for R1 and R2
Simulate each sample using spice
Determine gain for each sample
For each set of tolerance limits, determine yield loss and defect level.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

30. Monte Carlo Simulation Data
Slope = G R2 R1
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

31. ELEC 7770: Advanced VLSI Design (Agrawal)
Setting Test Limits
Minimize yield loss
Slope = G R2
Minimize defect level R1
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

32. ELEC 7770: Advanced VLSI Design (Agrawal)
Alternate Test
Besides components (e.g., R1 and R2 for operational amplifier) easily measurable parameters used for testing.
An example is the supply current IDD of the operational amplifier.
A simple test is to measure IDD(0) for 0V input.
Monte Carlo simulation is then used to set the limits on IDD(0).
Large number of sample circuits with component variations are simulated to determine thresholds for IDD(0).
Additional measurements can improve test.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

33. Alternate Test: Setting Thresholds
Minimize yield loss
Within
spec.
gain
Gain
Minimize defect level
Fail Pass Fail
IDD(0)
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

34. ELEC 7770: Advanced VLSI Design (Agrawal)
Zero Defect Level
Yield loss increased
Within
spec.
gain
Gain
Fail Pass Fail
IDD(0)
Zero defect level
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

35. ELEC 7770: Advanced VLSI Design (Agrawal)
Zero Yield Loss
Zero yield loss
Within
spec.
gain
Gain
Increased defect level
Fail Pass Fail
IDD(0)
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

36. ELEC 7770: Advanced VLSI Design (Agrawal)
References
P. N. Variyam, S. Cherubal and A. Chatterjee, “Prediction of Analog Performance Parameters Using Fast Transient Testing,” IEEE Trans. Computer-Aided Design, vol. 21, no. 3, pp , March 2002.
H.-G. Stratigopoulos and Y. Makris, “Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing,” IEEE Trans. Computer-Aided Design, vol. 27, no. 2, pp , February 2008.
Spring 2016, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)