ECE 331 – Digital System Design Latches and Flip-Flops (Lecture #17) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Fall 2010ECE Digital System Design2 Material to be covered … Chapter 11: Sections 1 – 7

Fall 2010ECE Digital System Design3 Brief introduction to Sequential Logic Circuits

Fall 2010ECE Digital System Design4 Sequential switching circuits have the property that the output depends not only on the present input but also on the past sequence of inputs. In effect, these circuits must be able to “remember” something about the past history of the inputs in order to produce the present output. We say a circuit has feedback if the output of one of the gates is connected back into the input of another gate in the circuit so as to form a closed loop. Sequential Logic Circuits

Fall 2010ECE Digital System Design5 Sequential Logic Circuits Combinational Logic Circuit Memory inputs outputs

Fall 2010ECE Digital System Design6 Basic Memory Elements

Fall 2010ECE Digital System Design7 Basic Memory Elements Latch  Clock input is level sensitive.  Output can change multiple times during a clock cycle.  Output changes while clock is active. Flip Flop  Clock input is edge sensitive.  Output can change only once during a clock cycle.  Output changes on clock transition.

Fall 2010ECE Digital System Design8 Basic Memory Elements Both latches and flip flops use feedback to achieve “memory”.

Fall 2010ECE Digital System Design9 Feedback Circuit with 2 Stable States What is the problem with this circuit?

Fall 2010ECE Digital System Design10 Set-Reset (SR) Latch P NOR gates Feedback

Fall 2010ECE Digital System Design11 SR Latch: Behavior

Fall 2010ECE Digital System Design12 SR Latch: Behavior

Fall 2010ECE Digital System Design13 S RQ+Q+ 0 Q Not allowed If S = 1 (Set), Q + = 1 If R = 1 (Reset), Q + = 0 If S = R = 0, Q + = Q (no change) S = R = 1 is not allowed. SR Latch: Behavior

Fall 2010ECE Digital System Design14 P ≠ Q′ SR Latch: Improper Operation

Fall 2010ECE Digital System Design15 SR Latch: Symbol always complementary

Fall 2010ECE Digital System Design16 SR Latch: Timing Diagram

Fall 2010ECE Digital System Design17 SR Latch: Characteristic Equation Characteristic Equation: Q + = S + R'.Q (S.R = 0)

Fall 2010ECE Digital System Design18 SR Latch: using NAND gates

Fall 2010ECE Digital System Design19 A gated D latch has two inputs – a data input (D) and a gate input (G). The D latch can be constructed from an S-R latch and additional logic gates. When G = 1, the value of D is passed to Q. When G = 0, the Q output holds the last value of D (no state change). This type of latch is also referred to as a transparent latch. Gated D Latch

Fall 2010ECE Digital System Design20 Gated D Latch: Circuit and Timing

Fall 2010ECE Digital System Design21 Gated D Latch: Symbol and Truth Table No invalid inputs!

Fall 2010ECE Digital System Design22 Gated D Latch: Characteristic Equation Characteristic Equation: Q + = G'.Q + G.D

Fall 2010ECE Digital System Design23 Gated D Latch: using NAND gates S' R'

Fall 2010ECE Digital System Design24 A D flip-flop has two inputs, D (data) and Ck (clock). The small arrowhead on the flip-flop symbol identifies the clock input. Unlike the D latch, the flip-flop output changes only in response to the clock, not to a change in D. If the output can change in response to a 0 to 1 transition on the clock input, we say that the flip-flop is triggered on the rising edge (or positive edge) of the clock. If the output can change in response to a 1 to 0 transition of the clock input, we say that the flip-flop is triggered on the falling edge (or negative edge) of the clock. An inversion bubble on the clock input indicates a falling-edge trigger. D Flip-Flop (edge-triggered)

Fall 2010ECE Digital System Design25 Q + = D Characteristic Equation D Flip-Flop

Fall 2010ECE Digital System Design26 D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on?

Fall 2010ECE Digital System Design27 D Flip-Flop (master-slave)

Fall 2010ECE Digital System Design28 D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on?

Fall 2010ECE Digital System Design29 D Flip-Flop: Setup and Hold Times

Fall 2010ECE Digital System Design30 D Flip-Flop: Minimum Clock Period

Fall 2010ECE Digital System Design31 Questions?