Latch versus Register  Latch stores data when clock is low D Clk Q D Q Register stores data when clock rises Clk D D QQ

Latches

Latch-Based Design N latch is transparent when  = 0 P latch is transparent when  = 1 N Latch Logic P Latch 

Timing Definitions t CLK t D t c 2 q t hold t su t Q DATA STABLE DATA STABLE Register CLK DQ

Positive Feedback: Bi-Stability V o 1 V i 2 5 V o 1 V i 2 5 V o 1 V i1 A C B V o2 V i1 =V o2 V o1 V i2 V i2 =V o1

Meta-Stability Gain should be larger than 1 in the transition region

Writing into a Static Latch D CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states

Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0D Q 0 1D Q

Mux-Based Latch

NMOS onlyNon-overlapping clocks

Master-Slave (Edge- Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair

Master-Slave Register Multiplexer-based latch pair

Clk-Q Delay

Setup Time

Reduced Clock Load Master-Slave Register

Avoiding Clock Overlap CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK

Other Latches/Registers: C 2 MOS “Keepers” can be added to make circuit pseudo-static

Insensitive to Clock-Overlap M 1 DQ M 4 M 2 00 V DD X M 5 M 8 M 6 V (a) (0-0) overlap M 3 M 1 DQ M 2 1 V DD X M 7 1 M 5 M 6 V (b) (1-1) overlap

Other Latches/Registers: TSPC Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1)

Including Logic in TSPC AND latch Example: logic inside the latch

TSPC Register

Pulse-Triggered Latches An Alternative Approach Master-Slave Latches D Clk QD Q Data D Clk Q Data Pulse-Triggered Latch L1L2L Ways to design an edge-triggered sequential cell:

Pulsed Latches Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :