1. EE141 © Digital Integrated Circuits 2nd Timing Issues 1 Latch-based Design

2. EE141 © Digital Integrated Circuits 2nd Timing Issues 2 Register Parameters D Clk Q Delays can be different for rising and falling data transitions D Q Clk t c-q t hold T t su

3. EE141 © Digital Integrated Circuits 2nd Timing Issues 3 Latch Parameters D Clk Q Delays can be different for rising and falling data transitions D Q Clk t c-q t hold PW m t su t d-q T

4. EE141 © Digital Integrated Circuits 2nd Timing Issues 4 Latch timing D Clk Q t D-Q t Clk-Q When data arrives to transparent latch - latch is a “soft” barrier When data arrives to closed latch - data has to be ‘re-launched’

5. EE141 © Digital Integrated Circuits 2nd Timing Issues 5 Flip-Flop – Based Timing Flip -flop Logic    Flip-flop delay Skew Logic delay T SU T Clk-Q Representation after M. Horowitz, VLSI Circuits 1996.

6. EE141 © Digital Integrated Circuits 2nd Timing Issues 6 Timing Constraints Minimum cycle time: T clk  t c-q + t su + t logic Basic constraints without clock skew and jitter Hold time constraint: t (c-q, cd) + t (logic, cd)  t hold

7. EE141 © Digital Integrated Circuits 2nd Timing Issues 7 Latch-Based Timing L1 Latch Logic L2 Latch    L1 latch L2 latch Skew Can tolerate skew! Long path Short path Static logic

8. EE141 © Digital Integrated Circuits 2nd Timing Issues 8 Synchronous Pipelined Datapath Logic Block #3 T CLK  T CLK Block #1 Block #2 Register based pipeline The computation between the registers must be completed within T clk

9. EE141 © Digital Integrated Circuits 2nd Timing Issues 9 Latch-Based Design L1 Latch Logic L2 Latch  L1 latch is transparent when  = 0 L2 latch is transparent when  = 1

10. EE141 © Digital Integrated Circuits 2nd Timing Issues 10 Register-based vs Latch-based Pipeline Register-based: using edge triggered registers Latch-based: using level transparent latches - break combinational logic in two blocks - replace register by two lathes and move second latch between the blocks Clk Logic Block 1 Logic Block 2 In Out L1a L1bL2a

11. EE141 © Digital Integrated Circuits 2nd Timing Issues 11 Latch-based Pipeline design CLK1 CLK2 T CLK  Nominal computation: Computation in each block is nominally performed in phase CLK=0 (block A computes when CLK1= 0, block B computes when CLK2=0) The entire computation of d must be ready by edge 4 => Delay =1.5 Tclk t pd,A In must be ready prior to CLK1=0 a valid t pd,B c valid d ready t su + t DQ CLB_ACLB_B Input b ready Q D In CLB_A Q DQD CLK1 L1 L2 L1 CLK2CLK1 CLB_B t pd,A t pd,B abcde

12. EE141 © Digital Integrated Circuits 2nd Timing Issues 12 Slack-borrowing CLK1 CLK2 T CLK  t pd,A a valid t DQ t pd,B b valid d valid t DQ e valid slack passed to next stage = slack c valid CLB_A computes CLB_B computes Actual computation can start earlier, when CLK=1, as long as data is available and stable (e.g. block A does not have to wait for CLK1 to be 0) Q D In CLB_A Q DQD CLK1 L1 L2 L1 CLK2CLK1 CLB_B t pd,A t pd,B abcde