PhD Student: Carlos Arthur Lang Lisbôa Advisor: Luigi Carro VLSI-SoC PhD Forum Low overhead system level approaches to deal with multiple and long duration transient faults in future technologies INFORMÁTICA Universidade Federal do Rio Grande do Sul - UFRGS Instituto de Informática, Pós-Graduação em Ciência da Computação Grupo de Microeletrônica (GME) - Laboratório de Sistemas Embarcados (LSE) Porto Alegre - RS BRAZIL Phone CMOS technologies beyond the 45 nm node will present devices that will be subject to radiation induced transients lasting longer than the predicted clock cycle of circuits. In this scenario, techniques based on temporal redundancy will no longer succeed, while those based on spatial redundancy will still imply high overheads. Therefore, innovative low cost techniques, working at system or algorithm level, will be required to cope with this type of faults. Prediction of Long Duration Transient (LDTs) [1] Vertical bars show predicted transient widths for 20 Mev-cm 2 /mg Lines show predicted cycle times for different inverter chains Duration of transients extracted from [2] and [3] Even low energy particles may cause long duration transients Why temporal redundancy schemes, such as [4, 5], will no longer succeed ? check the outputs twice samples separated by a delay delay must be longer than expected transient width long transients imply heavy penalties [1]Lisboa, C. A., and Carro, L. System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies, Proc. of 12 th European Test Symposium – ETS [2]Dodd, P. E., et al., Production and propagation of Single-Event Transients in High-Speed Digital Logic ICs, IEEE Tr. on Nuc. Science, Vol 51, No 6, Part 2, IEEE Comp. Soc., Los Alamitos, CA, Dec [3] Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy Ion and Proton Irradiation - Implications for Digital SETs, Ferlet-Cavrois et al, IEEE Tr. on Nuc. Sci., Vol. 53 No. 6, Nov [4]Anghel, L. and Nicolaidis, M., Cost Reduction and Evaluation of a Temporary Faults Detection Technique, in Proc. of Design, Automation and Test in Europe Conference (DATE 2000), ACM Press, New York, NY, USA, March, [5]S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, "Robust system design with built-in soft-error resilience", Computer, Vol. 38, No 2, A case study: low overhead error detection in matrix multiplication [1] (a) Hardware implementation (sequential circuit, 1120 lines of VHDL code, parameterized by n) (b) Software implementation Calculate: Vector Cr, where Cr i = C i1 + C i C in (1) Vector Br, where Br i = B i1 + B i B in (2) Vector ABr, where ABr i = n k=1 A ik. Br k (3) If ABr Cr, there was an error Future work Low cost recomputation techniques for matrix multiplication upon error detection Use of similar approaches to harden other frequently used algorithms for embedded systems Validation of the proposed techniques through application to harden a complete SoC Time comparison - software (number of * and + operations) Time comparison in s (*)