1. Carlos Arthur Lang Lisbôa, Luigi Carro, Erika Cota ETS 2005 RobOps - Arithmetic Operators for Future Technologies Future technologies, bellow 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, a different design approach must be taken. Porto Alegre - RS BRAZIL Phone +55 51 33166155 e-mail calisboa@inf.ufrgs.br carro@eletro.ufrgs.br erika@ @inf.ufrgs.br Universidade Federal do Rio Grande do Sul - UFRGS Pós-Graduação em Ciência da Computação Grupo de Microeletrônica (GME) Laboratório de Sistemas Embarcados (LSE) http://www.inf.ufrgs.br/gme, http://www.inf.ufrgs.br/~lse Bit Stream Representation of Products Conclusions  Multiplier’s tolerance to multiple simultaneous faults (up to 3 bit flips) already confirmed by experiments  When compared with TMR, proposed solution is faster and area is not an issue Table 2. Redundant Bits x Fault Tolerance Notes: “ r ” may be an odd number fault tolerance does not depend on the factors’ width ( f ); it depends on “ r ” the total quantity of bits that can change to 1 (w/o matching complementary flips) is 2 r-1 -1 the total quantity of bits that can change to 0 (w/o matching complementary flips) is 2 r-1 Who cares about multiple simultaneous transient faults ? TMR can not withstand multiple upsets Module 1 (faulty) wrong output Module 2 (no fault) correct output Module 3 (faulty) wrong output VOTERVOTER wrong output Introduction Fig. 2 – Adding robustness to the bit stream b48.. b48 b47.. b47... b0.. b0 1 1 1 1 0 0 0 8 times 8 times 8 times +4 total count of 1’s = 8 * product + 4 Sample 8-bit Stream Multiplier (RobOp) 64 robust 1-bit multipliers (see detail) generate the 15 “column bit streams” total of 512 AND gates (64 multipliers x 8 gates) each column stream is independent from those of the other columns (different weights) each column stream has 8 to 64 data bits plus 4 bits equal to 1 (see detail) total of 572 output bits (512 + 15 x 4) conversion to binary code (counting bits equal to 1 in the stream) postponed 7.06.05.04.03.02.01.00.0 7.16.15.14.13.12.11.10.1 7.26.25.24.23.22.21.20.2 7.36.35.34.33.32.31.30.3 7.46.45.44.43.42.41.40.4 7.56.55.54.53.52.51.50.5 7.66.65.64.63.62.61.60.6 7.76.75.74.73.72.71.70.7 12 V dd a.b 1111 Sample 5-tap FIR Filter using RobOps 5 robust multipliers generate 75 (5 x 15) product column streams each column in the filter shares the same 4 redundant bits (bits = 1) combinational circuits (cctr) count bits equal to 1 in each column stream 2 lsbits of the counters are discarded (pseudo division by 4) converter circuit adds bit counts from each column (according to their weights), thus generating the binary coded filter output product streams stand up to 3 bit flips in each column conversion from bit streams to binary code (counters and adders) not yet protected cctr converter Future Work  Counters and converter must be made tolerant to the same amount of multiple simultaneous faults  Implementation and test of the digital filter with the operators Fig. 1 – Proposed Multiplication Algorithm - bit stream product (the count of 1’s in the stream is equal to the product value) Table 1. Bit Stream Tolerance to Multiple Upsets ab