Presentation is loading. Please wait.

Presentation is loading. Please wait.

Advancement on the Analysis and Mitigation of

Published by Modified over 5 years ago

Similar presentations

Presentation on theme: "Advancement on the Analysis and Mitigation of"— Presentation transcript:

1 Advancement on the Analysis and Mitigation of
11th APRIL 2018 SpacE FPGA Users Workshop - SEFUW Advancement on the Analysis and Mitigation of SETs on Flash-based FPGAs Sarah Azimi1 Boyang Du1 Luca Sterpone1 David Merodio Codinachs2 Politecnico di Torino- CAD Group1 Dipartimento di Automatica e Informatica Torino- Italy European Space Agency2 The Netherlands

2 Motivations Space environment is characterized by several types of radiation particles: Heavy Ions Protons Neutrons Single Event Transient Effect Total Ionizing Dose Effect Single Event Latch-up Sarah Azimi - SEFUW Noordwijk - The Netherlands

3 Radiation effects on Flash-based technology
Motivations Radiation effects on Flash-based technology ProASIC3 RTG4 Examples of transient pulses generated by particle incident Flash-based FPGA Versatile of ProASIC3 Logic Element of RTG4 Sarah Azimi - SEFUW Noordwijk - The Netherlands

4 Current pulse generates a Single Event Transient - SET
Motivations Current pulse generates a Single Event Transient - SET SET may propagate through multiple circuit paths Generation of Multiple SEUs on registers SET generation SET propagation Multiple SEUs Computational Register (operand) Sarah Azimi - SEFUW Noordwijk - The Netherlands

5 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands
SET Characterization Focus of SET Characterization Analysis of SET propagation through Next combinational logics Routing resources Fan-out gate load Sarah Azimi - SEFUW Noordwijk - The Netherlands

6 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands
SET Generation Main methods to emulate SET pulses induced by particles striking the semiconductor of the devices: Radiation Test Laser Test In-Circuit Test Sarah Azimi - SEFUW Noordwijk - The Netherlands

7 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands
In-Circuit Test In-Circuit test generated pulse depends on: Routing delay Inverters Propagation time Signal Generator Routing Delay Routing Delay IN (SET Source) IN (SET Source) Routing Delay INVs Propagation Delay Signal Generator Pulse Pulse Width Pulse Width = ∆INV - ∆Routing Sarah Azimi - SEFUW Noordwijk - The Netherlands

8 Global developed methodology for SET characterization
Circuit under the test considering four different scenarios Path of Gates Path of Gates with Fanout Divergence Paths Convergence Paths In-Circuit Test Circuit Under the Test External SET measurement Pulse Generator Sarah Azimi - SEFUW Noordwijk - The Netherlands

9 Scenario 1 – Path of Gates
Characterization of logical gates Using several lengths of Inverter-string Injecting SET at the input of the strings Measuring SET at the end of the strings Internal Injector Inverter-String Signal Generator Output SET Sarah Azimi - SEFUW Noordwijk - The Netherlands

10 Scenario 1 – Path of Gates
Characterization of logical gates Placed side by side Minimal distance between each versatile Internal Injector Inverter String Microsemi Libero SoC 11.7 Commercial Design Tool Environment Placement Microsemi Libero SoC 11.7 Commercial Design Tool Environment Routing Sarah Azimi - SEFUW Noordwijk - The Netherlands

11 Scenario 1 – Path of Gates
Characterization of logical gates Four string with 40,60,80 and 100 Inverter gates By increasing string length, PIPB increases By increasing string length, delay increases INVs [#] Source SET [ns] Output SET [ns] PIPB Delay [ns] 40 7.2 1 6.8 60 8 1.11 10.2 80 10 1.25 18.4 100 7.4 8.8 1.18 30.4 Sarah Azimi - SEFUW Noordwijk - The Netherlands

12 Scenario 2 – Inverter Path with Fanout
Characterization of gates chain including various fanout Connecting fanout of inverters to the beginning of the string Minimal distance connection between each versatile Internal Injector Inverter-String Signal Generator Output SET Fanout Sarah Azimi - SEFUW Noordwijk - The Netherlands

13 Scenario 2 – Inverter Path with Fanout
Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 100 Inverters as string Sarah Azimi - SEFUW Noordwijk - The Netherlands

14 Scenario 2 – Inverter Path with Fanout
Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 40, 60, 80 and 100 Inverters as string Chain 40 Chain 60 Chain 80 Chain 100 PIPB Delay [ns] Sarah Azimi - SEFUW Noordwijk - The Netherlands

15 Scenario 2 – Inverter Path with Fanout
Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 40, 60, 80 and 100 Inverters as string Increasing PIPB by increasing the length of string Attenuating of PIPB by increasing fanout Chain 40 Chain 60 Chain 80 Chain 100 PIPB Delay [ns] Sarah Azimi - SEFUW Noordwijk - The Netherlands

16 By Increasing the fanout, the delay of the circuit is not changing
Scenario 2 – Inverter Path with Fanout Characterization of gates chain including various fanout 20, 40 and 60 Inverter gates as fanout 40, 60, 80 and 100 Inverters as string Increasing PIPB by increasing the length of string Attenuating of PIPB by increasing fanout By Increasing the fanout, the delay of the circuit is not changing Chain 40 Chain 60 Chain 80 Chain 100 PIPB Delay [ns] Sarah Azimi - SEFUW Noordwijk - The Netherlands

17 Scenario 3 – Divergence Paths
Characterization of SET while there is an occurrence of divergence of combinational paths Propagation of SET through multiple paths Divergence Point Path (A) SET (A) SET (B) Path (B) Sarah Azimi - SEFUW Noordwijk - The Netherlands

18 Scenario 3 – Divergence Paths
Characterization of SET while there is an occurrence of divergence of combinational paths Adding second inverter string in the middle of the main string Observing SET at the end of both strings Internal Injector Main Inverter-String Signal Generator Divergence Point Output SET (main) Output SET (Secondary) Secondary Inverter-String Sarah Azimi - SEFUW Noordwijk - The Netherlands

19 Scenario 3 – Divergence Paths
Characterization of SET while there is an occurrence of divergence of combinational paths 100 Inverter gates as main string 60, 80 and 100 Inverter gates as secondary string PIPB-main PIPB-Secondary PIPB Delay [ns] Number of INVs in the secondary string Number of INVs in the secondary string Sarah Azimi - SEFUW Noordwijk - The Netherlands

20 Scenario 4 – Convergence Paths
Characterization of SET while traversing through divergence point and uniting at convergence point Divergence Point Path (A) Convergence Point Path (B) Sarah Azimi - SEFUW Noordwijk - The Netherlands

21 Scenario 4 – Convergence Paths
Overlapping SET outcome at the convergence point Minimal difference on the propagation delay of two paths, SET with Extremely large width Time [ns] Voltage [v] Overlapped C-SET Large difference on the propagation delay of two paths, SET shapes are provided as two separate pulses Time [ns] Voltage [v] SET (A) SET (B) Delay (A) - Delay (B) Divergence Point Delay (A) Convergence Point Delay (B) Sarah Azimi - SEFUW Noordwijk - The Netherlands

22 Scenario 4 – Convergence Paths
Characterization of SET while traversing through divergence point A, propagate through different logical paths B, C and routings and reaching to the convergence point D. Internal Injector Main Inverter-String Signal Generator A Path (B) D Output SET (main) Path (C) Routing Delay Sarah Azimi - SEFUW Noordwijk - The Netherlands

23 Scenario 4 – Convergence Paths
SET outcome at the convergence point SET Guard Gate Filtering Delay (C) – Delay (B) Case (III) Delay (C) – Delay (B) Case (II) Delay (C) – Delay (B) Case (I) Max SET Width Delta Delay Case (III) Case (II) Case (I) Sarah Azimi - SEFUW Noordwijk - The Netherlands

24 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands
SETA Tool SETA: a CAD tool to evaluate the sensitivity of the implemented circuit regarding SET targeting SET propagation PIPB effect Sarah Azimi - SEFUW Noordwijk - The Netherlands

25 Convergence SET analyzer
C-SETA Tool C-SETA: a CAD tool to evaluate the sensitivity of the implemented circuit regarding Convergence-SET Microsemi Libero SoC Microsemi Libero SoC .pdc .sdf .v HDL Synthesized netlist Convergence SET analyzer (C-SETA) C-SET Error Occurrence Mapping Place and Route Sarah Azimi - SEFUW Noordwijk - The Netherlands

26 C-SETA on Real Scenarios
Analyzing the circuits SET sensitivity using SETA and C-SETA implemented on A3P250 Flash based FPGA Injecting SETs lower than 1 ns Characteristics of the Benchmark Circuits Circuits Versatile [#] FFs [#] Frequency [MHz] B05 415 66 47 B09 493 67 46 B12 565 123 48 B13 162 50 52 CORDIC 956 240 45 Sarah Azimi - SEFUW Noordwijk - The Netherlands

27 C-SETA on Real Scenarios
Analyzing the circuits SET sensitivity using SETA and C-SETA Implemented on A3P250 Flash based FPGA Injecting SETs lower than 1 ns Comprehensive SET Sensitivity Using SETA and C-SETA Tool Circuits Totally Filtered [#] Partially Filtered [#] Broadened [#] Possible C-SET [#event] B05 46 9 8 423 B09 47 3 11 29 B12 102 1 13 1665 B13 21 14 7 44 CORDIC 161 12 39 318 Sarah Azimi - SEFUW Noordwijk - The Netherlands

28 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands
Future Advancements Execution of radiation test for experimental validation of C-SET Application of C-SET technique to RTG4 family C-SET software delivery Supported by ESA under contract: SEE analysis and mitigation on SRAM and Flash-based FPGAs Sarah Azimi - SEFUW Noordwijk - The Netherlands

29 Sarah Azimi - SEFUW2018 - Noordwijk - The Netherlands
Thank You! Sarah Azimi - SEFUW Noordwijk - The Netherlands

Download ppt "Advancement on the Analysis and Mitigation of"

Similar presentations

1 A latch is a pair of cross-coupled inverters –They can be NAND or NOR gates as shown –Consider their behavior (each step is one gate delay in time) –From.

1 A latch is a pair of cross-coupled inverters –They can be NAND or NOR gates as shown –Consider their behavior (each step is one gate delay in time) –From.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 261 Lecture 26 Logic BIST Architectures n Motivation n Built-in Logic Block Observer (BILBO) n Test.
April 30, 2014 1 Cost efficient soft-error protection for ASICs Tuvia Liran; Ramon Chips Ltd.

April 30, Cost efficient soft-error protection for ASICs Tuvia Liran; Ramon Chips Ltd.
June 6, 20071 Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits Tomasz S. Czajkowski and Stephen D. Brown Department of Electrical.

June 6, Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits Tomasz S. Czajkowski and Stephen D. Brown Department of Electrical.
2007 MURI Review The Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits Matthew J. Gadlage 1,2, Ronald.

2007 MURI Review The Effect of Voltage Fluctuations on the Single Event Transient Response of Deep Submicron Digital Circuits Matthew J. Gadlage 1,2, Ronald.
Altera FLEX 10K technology in Real Time Application.

Altera FLEX 10K technology in Real Time Application.
Power Visualization, Analysis, and Optimization Tools for FPGAs Matthew French, Li Wang and Michael Wirthlin USC, Information Sciences Institute, BYU.

Power Visualization, Analysis, and Optimization Tools for FPGAs Matthew French, Li Wang and Michael Wirthlin USC, Information Sciences Institute, BYU.
Synchronous Digital Design Methodology and Guidelines

Synchronous Digital Design Methodology and Guidelines
March 16-18, 2008SSST'20081 Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Fan Wang Vishwani D. Agrawal Department of Electrical and Computer.

March 16-18, 2008SSST'20081 Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Fan Wang Vishwani D. Agrawal Department of Electrical and Computer.
A Delay-efficient Radiation-hard Digital Design Approach Using Code Word State Preserving (CWSP) Elements Charu Nagpal Rajesh Garg Sunil P. Khatri Department.

A Delay-efficient Radiation-hard Digital Design Approach Using Code Word State Preserving (CWSP) Elements Charu Nagpal Rajesh Garg Sunil P. Khatri Department.
Chapter 7 Design Implementation (II)

Chapter 7 Design Implementation (II)
Programmable logic and FPGA

Programmable logic and FPGA
Results of Heavy-Ion Broad and Micro Beam Testing of Flash Based FPGAs Radiation Testing SEFUW – Wednesday, September 17 th 2014 Adrian Evans, Dan Alexandrescu.

Results of Heavy-Ion Broad and Micro Beam Testing of Flash Based FPGAs Radiation Testing SEFUW – Wednesday, September 17 th 2014 Adrian Evans, Dan Alexandrescu.
Global Timing Constraints FPGA Design Workshop. Objectives  Apply timing constraints to a simple synchronous design  Specify global timing constraints.

Global Timing Constraints FPGA Design Workshop. Objectives  Apply timing constraints to a simple synchronous design  Specify global timing constraints.
1 Efficient Analytical Determination of the SEU- induced Pulse Shape Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station,

1 Efficient Analytical Determination of the SEU- induced Pulse Shape Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station,
A comprehensive method for the evaluation of the sensitivity to SEUs of FPGA-based applications A comprehensive method for the evaluation of the sensitivity.

A comprehensive method for the evaluation of the sensitivity to SEUs of FPGA-based applications A comprehensive method for the evaluation of the sensitivity.
1 Extending Atmel FPGA Flow Nikos Andrikos TEC-EDM, ESTEC, ESA, Netherlands DAUIN, Politecnico di Torino, Italy NPI Final Presentation 25 January 2013.

1 Extending Atmel FPGA Flow Nikos Andrikos TEC-EDM, ESTEC, ESA, Netherlands DAUIN, Politecnico di Torino, Italy NPI Final Presentation 25 January 2013.
1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.

1 5. Application Examples 5.1. Programmable compensation for analog circuits (Optimal tuning) 5.2. Programmable delays in high-speed digital circuits (Clock.
ATMEL ATF280E Rad Hard SRAM Based FPGA SEE test results Application oriented SEU Sensitiveness Bernard BANCELIN ATMEL Nantes SAS, Aerospace Business Unit.

ATMEL ATF280E Rad Hard SRAM Based FPGA SEE test results Application oriented SEU Sensitiveness Bernard BANCELIN ATMEL Nantes SAS, Aerospace Business Unit.
COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

Similar presentations

Ads by Google