1. A Delay-efficient Radiation-hard Digital Design Approach Using Code Word State Preserving (CWSP) Elements Charu Nagpal Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX

2. 2 Outline Motivation and Introduction Previous Work Nicolaidis et. al. (CWSP based) Our Approach System Level Circuit Level Radiation protection analysis Maximum glitch width Experimental Results Conclusions and Future Work

3. 3 Why radiation-hardening? Historically mainly used for space and military electronics Higher levels of radiation in space and combat environments Terrestrial electronics also becoming vulnerable Shrinking feature size and supply voltage Reduced capacitances means less charge is required to flip node voltage This has resulted in a renewed interest in radiation- hardened circuit design

4. 4 Effects of radiation particle strike Neutrons, protons and heavy cosmic ions Ions strike diffusion regions Deposit charge Result in voltage spike at the output of a gate This can flip the state of a memory cell (SEU) For a combinational gate, this spike (SET) may cause an incorrect value to be sampled by the latches or flip-flops of the design

5. 5 Modeling a radiation-strike Charge deposited ( Q ) at a node is given by where: L is Linear Energy Transfer (MeV-cm 2 /mg) t is the depth of the collection volume (µm) The resulting current pulse is traditionally described as where:   is the collection time constant   is the ion track establishment constant ( Q =100fC,   = 200ps and   = 50ps) time (ns) Iseu (µA)

6. 6 Previous Work Classification of techniques: Radiation-tolerant design Device level M. Takai et al. “Soft error susceptibility and immune structures in dynamic random access memories (DRAM’s) investigated by nuclear microprobes,” IEEE Trans. Nucl. Sci. Feb 1996 Circuit level Zhou et. al. “Transistor sizing for radiation hardening,” Proc. Int. Reliability Physics Symp. 2004 System level S. Mitra et. al. “Robust system design with built-in soft-error resilience," IEEE Computer Feb 2005 Redundancy based techniques (TMR) Hardware redundancy – space dimension Temporal redundancy – time dimension

7. 7 CWSP Element This paper is based on the use of Code Word State Preserving elements M. Nicolaidis, “Time redundancy based soft- error tolerance to rescue nanometer technologies,” VLSI Test Symposium, April 1999 What is a CWSP element and how does it work? a out An inverter a a*a* out CWSP element of an inverter out ab a*a* b*b* a a*a* b b*b* CWSP element of NAND2 out ab a b NAND2 gate

8. 8 How does the CWSP element work? Latch / FF Original Circuit Comb. block with k logic gates OUT Latch / FF Comb. block with k-1 logic gates CWSP of the k th gate Delay δ CW (inverter) P P*P* δ δ P*P* P CW OUT t1t1 t2t2 t3t3 functional path Delay of 2δ + D CWSP - D k in the functional path where D CWSP : delay of the CWSP element D k : delay of the k th gate Use only one type of CWSP element, that of an inverter Reduces speed degradation due to body effect Avoid the need to have a library of CWSP gates Need to implement the complement of the combinational function, however..

9. 9 Our Approach - Architecture Original Circuit FF LOGIC D OUT clk Modified FF LOGIC OUT δ CWSP of the inverter EQ P*P* P CW FF CW CW* clk clk_d EQGLB F 1 0 CW* EQGLB GLB FF clk EQGLB D EQ FF EQGLB EQGLB F FF LOGIC OUT Detect a radiation strike clk D Calculate the correct value Our Approach – Abstract Level

10. 10 OUT Our Approach - Timing clk D P*P* P OUT CW EQ clk_d EQGLB EQGLB F δ δ Modified FF δ CWSP of the inverter P*P* P CW CW* clk EQGLB CW* EQGLB D EQ clk_d EQ FF CW FF CW * X EQGLB F 0 EQGLB GLB FF clk EQGLB F 1 Probability of more than one radiation strike in 2 consecutive cycles is 10 -10. This is exploited by introducing the MUX shown

11. 11 Our Approach – Circuit details Modified FF LOGIC OUT δ CWSP of the inverter EQ P*P* P CW FF CW CW* clk clk_d EQGLB F 1 0 EQGLB CW* EQGLB GLB FF EQGLB F clk EQGLB D EQ FF

12. 12 Our Approach – Circuit details Circuit level design – Modified FF Modified FF clk EQGLB D CW * OUT

13. 13 Our Approach – Circuit details Architecture level design Show the low-level design for each component Modified FF LOGIC OUT δ CWSP of the inverter EQ P*P* P CW FF CW CW* clk clk_d EQGLB F 1 0 CW* EQGLB GLB FF EQGLB F clk EQGLB D EQ FF EQGLB P*P* P CW POLY2 P

14. 14 Our Approach – Circuit details EQ, EQGLB and EQGLB F EQGLB F EQ FF clk_d GLB FF clk 0 EQGLB EQGLB F CW OUT EQ clk_d EQGLB F 1 0 EQGLB GLB FF EQGLB F clk EQ FF CW OUT

15. 15 Analysis of radiation-hardening Analyze radiation strikes at various nodes Modified FF LOGIC OUT δ CWSP of the inverter EQ P*P* P CW FF CW CW* clk clk_d EQGLB F 1 0 CW* EQGLB GLB FF EQGLB F clk EQGLB D EQ FF EQGLB

16. 16 Maximum glitch width D MIN constraint Modified FF OUT δ CWSP of the inverter P*P* P CW CW* clk EQGLB CW* EQGLB D EQ clk_d EQ FF CW FF EQGLB F 1 0 EQ The input of the CWSP element should be stable for at least 2δ to harden against a glitch of size δ on any of the inputs of the CWSP element

17. 17 If there is a radiation-strike at the D input of the modified FF, CW* should be ready setup time units before the next positive edge of the system clock ‘clk’ Maximum glitch width D MAX constraint Modified FF OUT δ CWSP of the inverter P*P* P CW CW* clk EQGLB CW* EQGLB D EQ clk_d EQ FF CW FF EQGLB F 1 0 EQ

18. 18 Experimental Setup Circuit simulation is performed in SPICE 65nm BPTM model card is used V DD = 1V V T N = | V T P |= 0.22V Radiation strike was modeled as current source Q =100fC,   = 200ps and   = 50ps Q =150fC,   = 200ps and   = 50ps LGsynth93 and ISCAS85 benchmark circuits

19. 19 D MIN and D MAX constraints Using   = 200ps,   = 50ps For Q =100fC, δ= 500ps For Q =150fC, δ= 600ps ∆ = 405ps For Q =100fC, D MIN ≥1000ps For Q =150fC, D MIN ≥ 1200ps For Q =100fC, D MAX ≥1405ps For Q =150fC, D MAX ≥ 1605ps So, any design with D MIN > 1000 and D MAX > 1405 can be protected up to 500ps (for Q =100fC,   = 200ps and   = 50ps) For designs with D MIN < 1000ps and D MAX < 1405ps, protect up to: Brayton et. al. Delay balancing is done in industrial designs, D MIN = 80% D MAX time (ns) Gate output voltage (V)

20. 20 One copy for the entire circuit For every flip-flop in the circuit Area overhead Area overhead calculation Modified FF LOGIC OUT δ CWSP of the inverter EQ P*P* P CW FF CW CW* clk clk_d EQGLB F 1 0 CW* EQGLB GLB FF clk EQGLB D EQ FF EQGLB F EQGLB

21. 21 Delay overhead Delay for unprotected circuit D MAX + T setup + T CO = D MAX + 40ps + 69ps Delay for the protected circuit D MAX + T setup + T CO + D input_load = D MAX + 38ps + 76ps + 6.5ps D input_load is the increase in delay of the combinational circuit output (due to the increased load on the D- input of the modified flip-flop of our design)

22. 22 Experimental Results     Q =150fC,   = 200ps and   = 50ps D MIN ≥ 1200ps, D MAX ≥ 1605ps Circuit Area (Unhardened) Area (Hardened) Overhead (%) Dmax Delay (Unhardened) Delay (Hardened) Overhead (%) alu228.2537.2932.001624.541733.541745.040.66 alu453.8865.8822.271700.281809.281820.780.64 apex2399.67404.281.152069.552178.552190.050.53 C354097.83130.5333.431931.052040.052051.550.56 C6288223.59271.0921.245141.065250.065261.560.22 seq421.60473.5312.322936.803045.803057.300.38 C7552187.68347.6285.232472.792581.792593.290.45 C88036.1574.78106.831692.801801.801813.300.64 Average 39.31% 0.51%

23. 23 Experimental Results     Q =100fC,   = 200ps and   = 50ps D MIN ≥1000ps, D MAX ≥ 1405ps Circuit Area (Unhardened) Area (Hardened) Overhead (%) Dmax Delay (Unhardened) Delay (Hardened) Overhead (%) alu228.2536.3828.781624.541733.541745.040.66 alu453.8864.6620.021700.281809.281820.780.64 apex2399.67403.821.042069.552178.552190.050.53 C190843.6677.0176.381562.651671.651683.150.69 C354097.83127.1930.021931.052040.052051.550.56 C6288223.59266.2319.075141.065250.065261.560.22 C7552187.68331.2276.482472.792581.792593.290.45 C88036.1570.8395.911692.801801.801813.300.64 seq421.60468.2211.062936.803045.803057.300.38 C5315152.17315.63107.421475.911584.911596.410.73 dalu65.5987.0032.631489.091598.091609.590.72 Average 45.34% 0.56%

24. 24 Experimental Results For D MIN < 1000ps and D MAX < 1405ps, protect up to: Circuit Area (Unhardened) Area (Hardened) Overhead (%)Dmax Delay (Unhardened) Delay (Hardened) Overhead (%) Pulse Width apex3139.13208.5949.931230.121339.121350.620.86412.56 b11_opt_C55.43104.7088.901270.951379.951391.450.83432.97 C135546.0188.6592.671012.191121.191132.691.03303.60 C43215.1224.5862.541385.391494.391505.890.77490.19 C49946.0188.6592.671012.191121.191132.691.03303.60 ex5p178.18264.9048.671195.081304.081315.580.88395.04 k288.53151.3670.971170.341279.341290.840.90382.67 apex1111.43174.2656.39982.901091.901103.401.05288.95 ex4p17.5924.4038.66630.38739.38750.881.56112.69 Average 66.82% 0.99%

25. 25 Conclusions and Future Work With the proposed approach:     For Q =150fC (100fC),   = 200ps and   = 50ps delay overhead 0.51 (0.56)%, area overhead 39.31 (45.34)% For circuits with D MIN < 1000ps or D MAX < 1405ps Protect Delay overhead < 1%, for high – speed, delay critical applications Combine the proposed approach with gate sizing Attenuate glitch width using sizing Now δ is smaller, D MIN, D MAX smaller as well ApproachArea Ovh.Delay Ovh.Protection Proposed45.34%0.56%100% Mohanram et. al.42.95%2.80%90% Nicolaidis et. al.17.65%28.65%100%

26. 26 Thank You !