1. Arithmetic Operators Robust to Multiple Simultaneous Upsets
Carlos Arthur Lang Lisbôa, Luigi Carro
Universidade Federal do Rio Grande do Sul
Instituto de Informática and Departamento de Engenharia Elétrica
DFT 2004
Cannes, France, 12/10/2004
12/10/2004
DFT 2004

2. Summary Presentation purpose
Fault tolerance and error tolerance; multiple faults
Previous studies
CL2C/A adder
CL2C/M multiplier
The conventional multiplication process
Multiplication with bit stream generation
Theoretical results
MatLab simulations
CL2C/MAC Operator
Short term objectives (Luigi: manter algum ?)
12/10/2004
DFT 2004

3. Presentation Purpose
To introduce a problem to be solved: How to deal with the occurrence of multiple transient faults in arithmetic operators ?
To present te current state of some ideas to solve this problem
To discuss the ideas and obtain feed-back and suggestions
Discuss future development alternatives
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DFT 2004

4. Fault Tolerance
Fault tolerance is the ability of a system to continue correct operation of its tasks after hardware or software faults occur.
[Johnson, 1993]
Fault tolerance tries to provide reliable operation in the presence of life-time faults and/or externally induced transient errors. [Breuer e Gupta, 2004]
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5. Error Tolerance
A circuit is error tolerant with respect to an application if it contains defects that cause internal errors and might cause external errors, and the system that incorporates this circuit produces acceptable results.
[Breuer e Gupta, 2004]
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6. Why Multiple Simultaneous Faults ?
Future technologies, bellow 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors.
...
Since many soft errors might appear at the same time, a different design approach must be taken.
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7. Multiple Faults Sources
New technologies: few electrons/channel
SEU influence
electromagnetic noise influence
temperature influence
Zero-defect manufacturing processes
users’ demand
cost to achieve
parameters spread makes corner-cases based design more difficult
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8. How to deal with faulty technologies?
The design process must take technology into account
If a gate is going to eventually fail, it will have an statistic behavior
First idea: to use gates with known statistic behavior
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9. Former Studies Stochastic Operators [Gaines, 1969]
Stochastic adder simulation
“almost” exact: error by 1
Stochastic multiplier simulation
precision heavily dependent on the number of samples
Filter simulation using stochastic operators
multiplier and adder together do not provide enough precision for this application
Short paper presented at IOLTS 2004
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10. Random numbers generator (R)
Stochastic Operators
Random numbers generator (R)
Binary value (V)
Cmp
(V>R) n 1
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11. Stochastic Adder [Gaines, 1969]
psum = p3  p1 + (1- p3)  p2
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12. Stochastic Multiplier [Gaines, 1969]
factor 1
product
factor 2
pproduct = pfactor1  pfactor2
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13. FIR filter simulation output (multiplication with 8.192 samples)
Input Output Stochastic
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14. FIR filter simulation output (multiplication with 64k samples)
Input Output Stochastic
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15. FIR filter simulation output (multiplication with 1M samples)
Input Output Stochastic
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16. How to avoid the errors of the stochastic representation?
We need more precision
Which is the source of the errors ?
How to avoid them ?
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17. The Adder (CL2C/A)
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18. CL2C/A Adder (based on [Gaines, 1969])
poutput = psel.p1 + (1- psel).p2
se psel = 0,5, therefore
poutput = 0,5.(p1 + p2)
and the probability of the sum is
twice the probability of the output
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19. Using a LFSR to generate the random values
LFSR never reaches 0
28/63 bits 0
34/63 bits 1
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20. Using a binary counter to generate the values (ramp)
28/63 bits 0
35/63 bits 1
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21. CL2C/A adder: 35 + 21 = 56 2 x count of 1s in output = 56
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22. 2 x count of 1s in output = 50 (error = -1)
CL2C/A adder: = 51
(35 1s)
(25 1s)
(21 1s)
2 x count of 1s in output = 50 (error = -1)
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23. CL2C/A adder: 15 + 8 = 23 Count of 1s in output = 23 (exact),
but the bit stream length doubles
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24. The Multiplier (CL2C/M)
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25. Binary multiplication (2 bits x 2 bits) 3 x 3 = 9
1 1 x
(x23) (x22) (x21) (x20)
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26. Binary multiplication (2 bits x 2 bits) 3 x 3 = 8 (error: -11,1%)
1 1 x
(x23) (x22) (x21) (x20)
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27. Binary multiplication (2 bits x 2 bits) 3 x 3 = 11 (error: +22,2%)
1 1 x
(x23) (x22) (x21) (x20)
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28. Binary multiplication (2 bits x 2 bits) 3 x 3 = 1 (error: -88,9%)
1 1 x
(x23) (x22) (x21) (x20)
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29. Binary multiplication (2 bits x 2 bits) 3 x 3 = 3 (error: -33,3%)
1 1 x
(x23) (x22) (x21) (x20)
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30. “Conventional” Multiplier
A A0
x B B0
B0.A1 B0.A0
B1.A1 B1.A0
P P P P0
(x23) (x22) (x21) (x20)
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31. “Conventional” Multiplier
A A0
x B B0
Complexity increases with quantity of bits
Same for response time
P P P1 P0
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32. Multiplier that generates “bit stream”
lower complexity
lower response time
product bits must be counted
high “fan out” in “ms gates”
A A0
x B B0
B0.A1 B0.A0
B1.A1 B1.A0
P P P P0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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33. Effect of a “bit flip”: error = 11,1%
stream stands to pairs of comple-mentary “flips”
each “flip” without a matching com-plementary “flip”: error = 11,1%
A A0
x B B0
B0.A1 B0.A0
B1.A1 B1.A0
P P P P0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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34. Effect of fault at a gate: error = 11,1%
A A0
x B B0
B0.A1 B0.A0
B1.A1 B1.A0
P P P P0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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35. Effect of fault at a gate : error = 22,2%
A A0
x B B0
B0.A1 B0.A0
B1.A1 B1.A0
P P P P0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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36. Effect of fault at a gate: error = 44,4%
A A0
x B B0
B0.A1 B0.A0
B1.A1 B1.A0
P P P P0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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37. Multiplier (2 x 2 bits) in MaxPlusII (without gate redundancy)
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38. Multiplication with bit stream using redundant gates
A A0
x B B0
area increases very fast with the number of bits
uniform gate “fan out”
B0.A1 B0.A0
B1.A1 B1.A0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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DFT 2004

39. Effect of a “flip” or fault: error = 11,1%
A A0
x B B0
stands to any quantity of complementary “flips”
error is constant for each “flip” without a matching complementary “flip”
B0.A1 B0.A0
B1.A1 B1.A0
p8 p7 p6 p5 p4 p3 p2 p1 p0
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40. Multiplier (2 x 2 bits) in MaxPlusII (with gate redundancy)
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41. Product stream serialization (w/o counting)
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42. Products Simulation: 3 x 3 and 2 x 1
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43. Binary value obtained counting the 1s = 100100
Multiplication with 1 redundant bit per factor: instead of 3 x 3 = 9  6 x 6 = 36  4 = 9 x
(x25) (x24) (x23) (x22) (x21) (x20)
Bit stream (36 ones and 13 zeros):
Binary value obtained counting the 1s =
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44. Effect of “bit flips” on the bit stream
Bit stream (36 ones and 13 zeros):
Binary value obtained counting the 1s =
Divisions by “virtual shift right” (integer quocient)
without faults: 36  4 = 9
any quantity of complementary “flips”: 36  4 = 9
balance of up to 3 “positive flips”: 39  4 = 9
balance of up to 4 “negative flips”: 32  4 = 8
Note:
fault tolerance already much higher than that of parity based schemes, but error by 1 = 11,1% to 100%, depending on the product value
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45. Multiplication with 2 redundant bits/factor: instead of 3 x 3 = 9  12 x 12 = 144  16 = 9 x
Bit stream now has 144 ones and 81 zeros
Binary value obtained by counting 1s =
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46. Effect of “bit flips” on the bit stream
Bit stream now has 144 ones and 81 zeros
Binary value obtained by counting 1s =
Divisions by “virtual shift right” (integer quocient)
without faults: 144  16 = 9
any quantity of complementary “flips”: 144  16 = 9
balance of up to 15 “positive flips”: 159  16 = 9
balance of up to 16 “negative flips”: 128  16 = 8
Note:
Even with increased redundancy, the “error by 1” problem remains: = 11,1% to 100%, depending on the product value.
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47. Multiplication with 2 redundant bits/factor and “excess of 0
Multiplication with 2 redundant bits/factor and “excess of 0.5” in the product 3 x 3 = 9  12 x = 152  16 = 9,5 x
Bit stream now has 152 ones and 73 zeros
Binary value obtained by counting 1s =
In order to “add 8”, “turning on” this bit is enough;
in practice, there is no addition, only connections to Vdd.
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48. Effect of “bit flips” on the bit stream
Bit stream now has 152 ones and 73 zeros
Binary value obtained by counting 1s =
Divisions by “virtual shift right” (integer quocient)
without faults: 152  16 = 9
any quantity of complementary “flips”: 152  16 = 9
balance of up to 7 “positive flips”: 159  16 = 9
balance of up to 8 “negative flips”: 144  16 = 9 !
Note:
Now it is even better and still stands to multiple transient faults (or manufacturing errors ?) !!!
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49. Simulation with MatLab
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50. Number of redundant bits in the product versus tolerance to “flips”
f = factors’ width; r = # of redundant bits in the product
Notes:
“r” may be an odd number
fault tolerance does not depend on the factors’ width (f); it depends on “r”
the total quantity of bits that can change to 1 (w/o matching complementary flips) is 2r-1-1
the total quantity of bits that can change to 0 (w/o matching complementary flips) is 2r-1
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51. Concern: area overhead
f = factors’ width; r = # of redundant bits in the product;
p = maximum product; bs = bit stream size (with redundancy)
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52. CL2C/MAC Operator (target application: filters)
Purpose: to cascade several operations without converting the bit stream to a binary code.
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53. RobOp Simulation Results (3x3 multiplier, 6400 operations)
12/10/2004
DFT 2004