1. 1 A Design Approach for Radiation-hard Digital Electronics Rajesh Garg Nikhil Jayakumar Sunil P Khatri Gwan Choi Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX-77840

2. 2 Outline Introduction Introduction Objective Objective Previous Approaches Previous Approaches Our Approach Our Approach Results Results Conclusions Conclusions

3. 3 Introduction There has been significant interest in the radiation immunity of electronic circuits There has been significant interest in the radiation immunity of electronic circuits Historically mainly used for space and military electronics Historically mainly used for space and military electronics Higher levels of radiation in space and combat environments Higher levels of radiation in space and combat environments More recently, terrestrial electronics are also becoming vulnerable More recently, terrestrial electronics are also becoming vulnerable Shrinking feature size and supply voltages Shrinking feature size and supply voltages Reduced capacitances means less charge is required to flip node voltage Reduced capacitances means less charge is required to flip node voltage This has led to a renewed interest in radiation tolerant circuit design This has led to a renewed interest in radiation tolerant circuit design

4. 4 Introduction (contd.) Effects of radiation particle strike Effects of radiation particle strike Neutron, proton and heavy cosmic ions Neutron, proton and heavy cosmic ions Ions strike diffusion regions Ions strike diffusion regions Deposit charge Deposit charge Results in a voltage spike Results in a voltage spike What is Single Event Upset (SEU)? What is Single Event Upset (SEU)? Interaction of a radiation particle with VLSI circuits can produce a charge deposition in critical regions of the circuit, leading to a bit reversal error, or single event upset. Interaction of a radiation particle with VLSI circuits can produce a charge deposition in critical regions of the circuit, leading to a bit reversal error, or single event upset.

5. 5 Introduction (contd.) Charge deposited ( Q ) at a node is given by Charge deposited ( Q ) at a node is given by where: L is Linear Energy Transfer (MeV/cm 2 /mg) t is the depth of the collection volume (mm) t is the depth of the collection volume (mm) Resulting current pulse is modeled as Resulting current pulse is modeled as where:   is the collection time constant where:   is the collection time constant   is the ion track establishment constant   is the ion track establishment constant

6. 6 Objectives Radiation particles cause SEU Radiation particles cause SEU Terrestrial electronics are also susceptible to SEU Terrestrial electronics are also susceptible to SEU Therefore, need circuit level protection against SEU even for consumer electronics Therefore, need circuit level protection against SEU even for consumer electronics To make circuit radiation tolerant To make circuit radiation tolerant Delay and area overhead should be minimized Delay and area overhead should be minimized

7. 7 Previous Approaches Transistor sizing is done to improve the radiation tolerance of the design (Zhou et. al) Transistor sizing is done to improve the radiation tolerance of the design (Zhou et. al) Ensure that capacitance of any node is sufficient to make the circuit radiation tolerant. Ensure that capacitance of any node is sufficient to make the circuit radiation tolerant. SEU event is detected using built in current sensor (BICS) (Gill et. al) SEU event is detected using built in current sensor (BICS) (Gill et. al) Triple modulo redundancy based approach (Neumann et. al) Triple modulo redundancy based approach (Neumann et. al) Error correction codes (Gambles et. al) Error correction codes (Gambles et. al) More detailed references can be found in the paper More detailed references can be found in the paper

8. 8 Our Radiation Hardening Approach Part 1: Gate Level SEU protection Part 1: Gate Level SEU protection Approach A: PN Junction Diode based SEU Clamping Circuits Approach A: PN Junction Diode based SEU Clamping Circuits Approach B: Diode-connected Device based SEU Clamping Circuits Approach B: Diode-connected Device based SEU Clamping Circuits Part 2: Logic Block Level Protection Part 2: Logic Block Level Protection Radiation hardening for all gates Radiation hardening for all gates Fixed depth protection Fixed depth protection Variable depth protection Variable depth protection

9. 9 Our Radiation Hardening Approach Approach A - PN Junction Diode based SEU Clamping Circuits Approach A - PN Junction Diode based SEU Clamping Circuits G GP in 1V 0V 1.4V -0.4V outP out D2 D1 Higher V T device Radiation Strike V (out) time 0 0.2 0.4 0.6 0.8 V (outP) time 0 0.2 0.4 0.6 0.8 -0.4 Shadow Gate

10. 10 Our Radiation Hardening Approach Approach B - Diode-connected Device based SEU Clamping Circuits Approach B - Diode-connected Device based SEU Clamping Circuits G GP in 1V 0V 1.4V -0.4V outP out D2 D1 Higher V T device Radiation Strike V (out) time 0 0.2 0.4 0.6 0.8 V (outP) time 0 0.2 0.4 0.6 0.8 -0.4 I ds

11. 11 Our Radiation Hardening Approach Compared approaches A and B Compared approaches A and B Performed layout and spice level simulation Performed layout and spice level simulation Approach A has higher area penalty than B Approach A has higher area penalty than B But performance of approach A is slightly better than B But performance of approach A is slightly better than B Therefore, selected approach B Therefore, selected approach B

12. 12 Simulating a Radiation Strike Circuit simulation is performed in SPICE Circuit simulation is performed in SPICE 65nm BPTM model card is used 65nm BPTM model card is used V DD = 1V V DD = 1V V T N = | V T P | = 0.22V V T N = | V T P | = 0.22V The radiation strike was modeled as current source The radiation strike was modeled as current source As commonly done in this field (Zhou et. al) As commonly done in this field (Zhou et. al) Varied the value of Q and   Varied the value of Q and     is chosen to be 5ps (Gill et. al)   is chosen to be 5ps (Gill et. al)

13. 13 Simulating a Radiation Strike Injected Current as a function of Q and   Injected Current as a function of Q and  

14. 14 Protection Performance - Example Radiation strike at output node. Radiation strike at output node. Q = 4 fC Q = 4 fC    10ps    10ps Approach B is used Approach B is used

15. 15 Block Level Radiation Hardening Individual gate protection Individual gate protection Approach B is selected Approach B is selected Area overhead is more than 100% Area overhead is more than 100% But our goal is to protect the entire logic circuit But our goal is to protect the entire logic circuit We call it as block level protection We call it as block level protection To understand block level protection To understand block level protection Critical depth of a gate Critical depth of a gate

16. 16 Critical Depth of a Gate Consider 2 input AND gate Consider 2 input AND gate Computed for each hardened cell Computed for each hardened cell 1 1 1 1 1 Radiation Strike Produces glitch Magnitude of glitch reduces Glitch magnitude is tolerable Critical Depth =3

17. 17 Critical Depth of a Gate Spice simulations were performed using Spice simulations were performed using Q = 5 fC,    10ps,    5ps Tolerable glitch magnitude is 0.35*V DD Tolerable glitch magnitude is 0.35*V DD Gate Name Critical Depth (Δ) inv2AA5 inv4AA1 nand2AA1 nand3AA1 nand4AA1 nor2AA1 nor3AA1 nor4AA1 and2AA2 and3AA1 and4AA1 or2AA1 or3AA1 or4AA1

18. 18 Block Level Radiation Hardening Simple approach – radiation hardening for all gates Simple approach – radiation hardening for all gates Very inefficient approach Very inefficient approach Large delay and area overhead Large delay and area overhead Primary Inputs Primary Outputs

19. 19 Block Level Radiation Hardening Better approach – Fixed depth protection Better approach – Fixed depth protection Let Δ max = max C (Δ(C)) Let Δ max = max C (Δ(C)) Assume Δ max = 2 then Assume Δ max = 2 then Primary Inputs Primary Outputs Radiation Strike

20. 20 Block Level Radiation Hardening Further improvement – Variable depth protection Further improvement – Variable depth protection Primary Inputs Primary Outputs

21. 21 Variable Depth Protection Let Δ(INV2AA) = 4, Δ(NAND2AA) = 1 and Δ(AND2AA) = 2 Let Δ(INV2AA) = 4, Δ(NAND2AA) = 1 and Δ(AND2AA) = 2 Maximum depth of protection required is 4 Maximum depth of protection required is 4 More details of the algorithm can be found in the paper More details of the algorithm can be found in the paper Primary Inputs Primary Outputs 1 2 3 4 5 6 7 8 9 10

22. 22 Experiments Used our approach on some benchmark circuits. Used our approach on some benchmark circuits. Used SIS for synthesis and technology mapping. Used SIS for synthesis and technology mapping. Circuits were mapped for both delay and area. Circuits were mapped for both delay and area. Used the “sense” package in SIS to find circuit delays. Used the “sense” package in SIS to find circuit delays. sense reports the largest sensitizeable delay. sense reports the largest sensitizeable delay. To get accurate area estimates, circuits were placed and routed using SEDSM from Cadence. To get accurate area estimates, circuits were placed and routed using SEDSM from Cadence. QPLACE for placement, WROUTE for routing QPLACE for placement, WROUTE for routing

23. 23 Delay Characteristics of the Cells CellRegular (ps)Hardened (ps)% Ovh Critical Depth inv2AA24.61428.0123.45 inv4AA23.91423.576-0.341 nand2AA31.41634.9933.581 nand3AA44.9248.393.471 nand4AA62.43666.2593.821 nor2AA45.61749.9024.291 nor3AA77.15182.7865.641 nor4AA92.8036495.384722.581 and2AA57.47661.9114.442 and3AA76.90282.7225.821 and4AA98.752107.3298.581 or2AA71.16174.6783.521 or3AA112.871116.3043.431 or4AA125.165128.5433.381 AVG3.97

24. 24 Block Level Delay Results Delay overhead primarily due to increased capacitive load from hardended cells. Delay overhead primarily due to increased capacitive load from hardended cells. Delay Overhead Area MappedDelay Mapped Ckt.RegularHardened% OvhRegularHardened%Ovh alu21057.991068.9131.03959.113976.9871.86 alu41318.6521357.8512.971247.7621259.6950.96 C1355887.619920.1863.67711.149720.3451.29 C19081301.5221349.0723.651085.281093.790.78 C35401546.8191625.4725.081414.4431424.7820.73 C499887.619920.1863.67711.149720.3451.29 C8801489.531643.5110.341405.3221554.84710.64 dalu1167.8171252.6087.261056.5341077.1341.95 frg2825.852912.60510.5792.849836.4775.5 i2451.879463.9492.67363.611382.2985.14 i3172.865184.7776.89172.865184.7776.89 C75522012.9242100.0944.332005.3712070.4913.25 i101997.3022253.8112.841931.2112002.743.7 AVG5.763.38

25. 25 Block Level Area Results Area overhead is larger for circuits mapped for minimum area Area overhead is larger for circuits mapped for minimum area Area overhead is also large for circuits with smaller logic depth (such as frg2 ) Area overhead is also large for circuits with smaller logic depth (such as frg2 ) Area Overhead Area MappedDelay Mapped Ckt.RegularHardened% OvhRegularHardened%Ovh alu21045.881728.965.311439.441728.920.11 alu42019.62830.2440.142470.093343.1535.35 C13551592.012252.4541.481728.92279.1131.82 C19081569.742252.4543.491799.462279.1126.66 C354031364763.7651.914022.15077.9926.25 C4991569.742265.7644.341728.92279.1131.82 C8801045.881883.5680.091397.262252.4561.2 dalu2470.093540.2543.323310.853986.6620.41 frg21994.524725.19136.912611.214057.6955.4 i2686.61745.298.55872.61948.648.71 i3495.51586.6118.39495.51566.4414.32 C75527032.512638.2679.717953.079576.5820.41 i106845.9960440.287705.3211291.1846.53 AVG53.3730.68

26. 26 Conclusions, Future Work We have presented a novel circuit design approach for radiation hardened circuit design. We have presented a novel circuit design approach for radiation hardened circuit design. We use shadow gates and protecting diode-connected devices to protect the primary gate from a radiation strike. We use shadow gates and protecting diode-connected devices to protect the primary gate from a radiation strike. We presented techniques to replace fewer gates to help minimize the area and delay penalties. We presented techniques to replace fewer gates to help minimize the area and delay penalties. Only 30% area penalty and 4% delay penalty on average for circuits mapped for minimum delay. Only 30% area penalty and 4% delay penalty on average for circuits mapped for minimum delay. In the future we hope to be able to incorporate radiation hardening in the technology mapping step itself. In the future we hope to be able to incorporate radiation hardening in the technology mapping step itself.

27. 27 Thank You!! Thank You!!

28. 28 Our Radiation Hardening Approach Radiation strike at the output of the shadow gate Radiation strike at the output of the shadow gate Output is protected upto 0.4+0.6+0.35 V glitch Output is protected upto 0.4+0.6+0.35 V glitch G GP in 1V 0V 1.4V -0.4V outP out D2 D1 Radiation Strike V (out) time 0 0.2 0.4 0.6 0.8 V (outP) time 0 0.2 0.4 0.6 0.8 -0.4 Shadow Gate

29. 29 Our Radiation Hardening Approach Radiation strike at the output of the shadow gate Radiation strike at the output of the shadow gate G GP in 1V 0V 1.4V -0.4V outP out D2 D1 Radiation Strike V (out) time 0 0.2 0.4 0.6 0.8 V (outP) time 0 0.2 0.4 0.6 0.8 -0.4 Shadow Gate