1. Carlos Arthur Lang Lisbôa, Luigi Carro DATE 2006 - EDAA PhD Forum Dealing with Multiple Simultaneous Faults in Future Technologies INFORMÁTICA Universidade Federal do Rio Grande do Sul - UFRGS Instituto de Informática, Pós-Graduação em Ciência da Computação Grupo de Microeletrônica (GME) - Laboratório de Sistemas Embarcados (LSE) http://www.inf.ufrgs.br/gme, http://www.inf.ufrgs.br/~lse Porto Alegre - RS BRAZIL Phone +55 51 33166155 e-mail calisboa@inf.ufrgs.br carro@eletro.ufrgs.br Future technologies, bellow 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might occur at the same time, a new design approach must be taken. Application to actual processors Low cost redundancy Stochastic Operators Bit Stream Operators Logic Properties DSP / VLIW previous work (2004-2005)2006 2007 Analog Voter Reconfig. Logic Double Fault Tolerance Research Plan Motivation propagation delays will be shorter than transient pulses duration smaller transistors will be more sensitive to electromagnetic noise and neutron and alpha particles industry experts believe that the probability of more than two simultaneous faults is neglectable the classic Triple Modular Redundancy approach can not withstand more than one fault at a time Single Event Upset Origin 0 1 0 1 1 1 1 01 1 0 1 1 1 1 0 1 0 1 0 0 0 0 1 (1)Lisbôa, C. and Carro, L., “An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets ”, in Proceedings of the 10th IEEE International Online Test Symposium - IOLTS 2004, pp. 180, IEEE Computer Society, New York, July 2004. (2)Lisbôa, C. and Carro, L., “Arithmetic Operators Robust to Multiple Simultaneous Upsets”, in Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - DFT 2004, pp. 289-297, ISBN 0-7695-2241-6. IEEE Computer Society, New York, October 2004. (3)Lisbôa, C. and Carro, L., “Highly Reliable Arithmetic Multipliers for Future Technologies”, in Proceedings of the International Workshop on Dependable Embedded Systems - WDES 2004 - in conjunction with the 23rd International Symposium on Reliable Distributed Systems - SRDS 2004, pp. 13-18. Edited by Becker, L. B. and Kaiser, J., Florianópolis, October 17, 2004. (4)Lisbôa, C., Carro, L., and Cota, E. “RobOps – Arithmetic Operators for Future Technologies”, in Informal Proceedings of the 10 th IEEE European Test Symposium (ETS 05), Tallinn, Estonia, May 2005. (5)Lisbôa, C., Schüler, E. and Carro, L., “Going Beyond TMR for Protection Against Multiple Faults”, in Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design, pp 80-85, 2005, Florianópolis, Brazil, September 04 - 07, 2005, ISBN:1-59593-174-0, ACM Press, New York, NY, USA, 2005. Using Stochastic Operators (1) Due to the random nature of SEU induced transient errors, stochastic operators have been chosen to implement one adder and one multiplier that could withstand multiple soft errors. Instead of adding or multiplying binary coded values, those devices operate on bit streams, whose probabilities (% of bits equal to 1 in the stream) are related to the values of the operands. There is an intrinsic approximation error in the conversion, which decreases as the number of bits in the stream increases, and can be regarded as noise. 8,192 samples % Errors in 1,000 additions Comments  Despite the low speed obtained in the simulation of a FIR Filter using the stochastic operators, we believe that the use of signal redundancy may lead to other interesting approaches  Also, the idea of taking component variability into account during design may succeed, once the adequate granularity to apply this approach is reached  In order to confirm those assumptions, new experiments are being developed in our research group 0 faults2 faults4 faults8 faults 0.14120.25800.17680.2196 StochasticConventional no faults 0.0000 Stochastic Adder Circuit 01100010101 010111011001 S1S1 S3S3 Sum 01010101101 0010100110101 S2S2 Stochastic Multiplier Circuit 1000100110011010 1001000100001011 1000000100001010  the precision of the output stream generated by the multiplier depends heavily on the stream length  short streams (with few samples) did not produce precise results  these operators have been used to implement a FIR filter (see figures) and, for this specific application, did not produce enough precision Output of FIR Filter Using the Stochastic Operators 1,048,576 samples Using Bit Stream Operators (2, 3, 4) The Analog Voter (5) The Problem In TMR based systems, the voter is a critical component, because: a single fault in the voter circuit may propagate to the output two or more simultaneous faults in the voter circuit may lead to erroneous voting output Proposed Solution Using some knowledge from the analog field, replace the digital voter with an analog comparator, since: analog design has been dealing with noise problems for many years transient events effects can be regarded as noise injection of transient faults can be simulated using current sources Injection of Faults in the Analog Voter During Test Extending the solution for n-MR Simulation Results: (a) multiple faults injection, (b) Montecarlo parameter variation (b) (a) 5-tap Filter using RobOps cctr converter Sample 8-bit Stream Multiplier (RobOp) 7.06.05.04.03.02.01.00.0 7.16.15.14.13.12.11.10.1 7.26.25.24.23.22.21.20.2 7.36.35.34.33.32.31.30.3 7.46.45.44.43.42.41.40.4 7.56.55.54.53.52.51.50.5 7.66.65.64.63.62.61.60.6 7.76.75.74.73.72.71.70.7 12 V dd a.b 1111 ab Bit Stream Representation of ProductsBasic Concepts  the multiplier generates a bit stream in which the number of bits equal to 1 is the value of the product  adding signal redundancy to this bit stream, tolerance to multiple bit flips in the stream is achieved  the stream is tolerant to a “balance” of flips which depends on the redundancy added to the stream (see Table 1) Fig. 2 – Adding robustness to the bit stream through redundancy b48.. b48 b47.. b47... b0.. b0 1 1 1 1 0 0 0 8 times 8 times 8 times +4 total count of 1’s = 8 * product + 4 Fig. 1 – Proposed Multiplication Algorithm - bit stream product (the count of 1’s in the stream is equal to the product value) F1 2 1 0 x F2 2 1 0 0. F1 2 F2 0. F1 1 F2 0. F1 0 F2 1. F1 2 F2 1. F1 1 F2 1. F1 0 F2 2. F1 2 F2 2. F1 1 F2 2. F1 0 b48.. b33b32.. b17b16.. b5b4.. b1b0 Comments  the exact sum of values represented by bit streams can be obtained simply by concatenating the streams corresponding to the values of the summands  as long as the values are kept as streams, they are protected against faults Conclusions  the main drawback of this approach is that the size of the bit streams grows very fast, but this should be ok for SET, for example  further research is being conducted in order to develop circuits to convert the streams into binary values with tolerance to multiple simultaneous faults