9-Oct-2002Prasad et al., ITC'021 A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets A. V. S. S. Prasad Agere Systems, Bangalore , India Vishwani D. Agrawal Agere Systems, Murray Hill, NJ 07974, USA Madhusudan V. Atre Agere Systems, Bangalore , India

9-Oct-2002Prasad et al., ITC'022 Talk Outline Introduction –Background –Problem statement A new graph model –Dominance graph –Transitive closure –Extraction of equivalence and dominance sets Functional equivalence Hierarchical fault collapsing Benchmark results Conclusion

9-Oct-2002Prasad et al., ITC'023 Test Vector Generation Flow DUT Generate fault list Collapse fault list Generate test vectors Fault Model Required fault coverage

9-Oct-2002Prasad et al., ITC'024 Background Single stuck-at fault model is the most popularly used model. Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2 (f1=f2) If all tests of fault f1 also detect fault f2, then f2 is said to dominate f1 (f1  f2). a 0 a 1 b 0 b 1 c 0 c 1 a 1  c 1 : Dominance b 1  c 1 : Dominance a 0 = b 0 = c 0 : Equivalence

9-Oct-2002Prasad et al., ITC'025 Background Both equivalence and dominance relations are transitive in nature. [ (f1  f2) and (f2  f3) => (f1  f3) ] If f1 dominates f2 and f2 dominates f1 then f1 and f2 are equivalent. [ (f1  f2) and (f2  f1) => (f1 = f2) ] Number of faults in a 2-input AND gate reduces from 6 to 4 (by equivalence) and to 3 (by dominance) collapsing. Example: ISCAS’85 Circuit - C6288, #faults = 10630, #faults (dominance collapsed) = 5824

9-Oct-2002Prasad et al., ITC'026 Problem Statement To devise a new method for fault collapsing with following attributes: –A single procedure for equivalence and dominance –Global analysis (independence from direction, and other choices, in collapsing) –Functional equivalence –Hierarchical fault collapsing (collapsing in large circuits using pre-collapsed sub networks)

9-Oct-2002Prasad et al., ITC'027 A fault in the circuit is represented by a node in the graph. A directed edge from f2 to f1 indicates that f1 dominates f2 (f2  f1). Edges can represent either structural or functional relations. A New Dominance Graph Model

9-Oct-2002Prasad et al., ITC'028 Computational Model Graph is represented as a connectivity matrix Each fault is assumed to be equivalent to itself Treats functional and structural relations identically (f1  f2) and (f2  f1) => f2 = f1. Appear as symmetrical components in the matrix (e.g., a 0,b 0,c 0 ) #faults = 6 (dimension of dominance matrix) 2-input AND gate

9-Oct-2002Prasad et al., ITC'029 Transitive Closure Transitive closure (TC) of the dominance matrix gives all dominance relations between faults. TC is computed by the O(n 3 ) Floyd- Warshall algorithm, where n is the dimension of the dominance matrix.

9-Oct-2002Prasad et al., ITC'0210 Transitive Closure (F1  F2) and (F2  F3) => (F1  F3) F1F1 F2F2 F3F3 F1F2F3 F1 11 F2 11 F3 1 Graph F1F1 F2F2 F3F3 F1F2F3 F1 111 F2 11 F3 1 Transitive Closure

9-Oct-2002Prasad et al., ITC'0211 Example A B C D E A0A0 B0B0 D0D0 E0E0 C0C0 A1A1 B1B1 D1D1 E1E1 C1C1 Dominance Graph Transitive closure edges

9-Oct-2002Prasad et al., ITC'0212 XOR Circuit Functional Equivalences : (c 1,f 1 ), (g 1,h 1,i 1 ), (g 0,m 0 ) c1c1 f1f1 g1g1 h1h1 i1i1 g0g0 m0m0

9-Oct-2002Prasad et al., ITC'0213 Dominance matrix (XOR) (24x24) Functional equivalences shown as boxed entries

9-Oct-2002Prasad et al., ITC'0214 Transitive Closure (XOR) j 0 k 0 m 1 f 1 f 0 …c 1 a 0

9-Oct-2002Prasad et al., ITC'0215 Results for XOR Circuit #faults#Eq. Faults#Dom. faults With functional equivalence #Dom. faults#Eq. Faults#faults

9-Oct-2002Prasad et al., ITC'0216 Summary of Approach Identify all the primary relations (structural and functional) Construct the dominance graph and represent the same using connectivity matrix Compute Transitive Closure (TC) Extract equivalence and dominance sets from TC

9-Oct-2002Prasad et al., ITC'0217 Features Global in nature (single procedure to treat equivalence and dominance collapsing) Functional relations can easily be incorporated Independent of the order of selecting the faults

9-Oct-2002Prasad et al., ITC'0218 Design Hierarchy Large designs are modular and hierarchical. Advantageous to store the fault information of repeated blocks in a library. When configured as a library cell the fault list includes cell PI & PO faults for transitivity. Top module B1 B0 C0 C1 C0 C1

9-Oct-2002Prasad et al., ITC'0219 XOR Library Cell Useful for hierarchical fault collapsing Dimension of the matrix = 14

9-Oct-2002Prasad et al., ITC' bit Ripple Carry Adder (RCA)

9-Oct-2002Prasad et al., ITC'0221 Faults in 8-bit RCA Number of collapsed faults Flat structural only Hierarchical with functional Equ.Dom.Equ.Dom. Xor cell Full-adder bit adder Circuit name All faults

9-Oct-2002Prasad et al., ITC'0222 ISCAS’85 Circuits Circuit name Total faults Equivalence fault set sizeDominance fault set size Graph methodOther programs*Graph methodFastest C C C432exp C C499exp C C C C C C C * Fastest, Gentest, Hitec, TetraMax

9-Oct-2002Prasad et al., ITC'0223 Conclusion A new algorithm for global fault collapsing With functional equivalence number of faults for ATPG reduces considerably Library based hierarchical fault collapsing is a new concept Further studies are being carried out on: –Functional dominance –Independent fault sets