1. Using Hierarchy in Design Automation: The Fault Collapsing Problem Raja K. K. R. Sandireddy Intel Corporation Hillsboro, OR 97124, USA raja.sandireddy@intel.comaja.sandireddy@intel.com Vishwani D. Agrawal Auburn University Auburn, AL 36849, USA vagrawal@eng.auburn.edu 11 th VLSI Design and Test Symposium Kolkata, August 8-11, 2007

2. Aug. 8, 2007VDAT: Sandireddy & Agrawal2 Outline Introduction –Main idea –Background on fault collapsing Hierarchical fault collapsing –Method –Advantages: Smaller collapse ratio Reduced CPU time Results Conclusion

3. Aug. 8, 2007VDAT: Sandireddy & Agrawal3 The General Idea of Hierarchy Circuit (top level In hierarchy) Subnetwork analyzed once, placed in library. interconnects Lowest-level block (gates and interconnects), analyzed in detail, saved in library. Analysis at n th level:1. Copy preprocessed internal detail of n-1 level from library. 2. Process n th level interconnects.

4. Aug. 8, 2007VDAT: Sandireddy & Agrawal4 Background on Fault Collapsing DUT Generate fault list Collapse fault list Generate test vectors Fault model Required fault coverage Test Vector Generation Flow

5. Aug. 8, 2007VDAT: Sandireddy & Agrawal5 Structural Fault Collapsing Equivalence Collapsing: It is the process of selecting one fault from each equivalence fault set. –Equivalence collapsed set = {a 0, b 0, c 0, c 1 } –Collapse ratio = 4/6 = 0.67 Dominance Collapsing: From the equivalence collapsed set, all dominating faults are left out retaining their respective dominated faults. – Dominance collapsed set = {a 0, b 0, c 1 } –Collapse ratio = 3/6 = 0.5 Total faults = 6

6. Aug. 8, 2007VDAT: Sandireddy & Agrawal6 An Example of Structural Collapsing a e c a 0 a 1 b0 b1b0 b1 c 0 c 1 d f d 0 d 1 f0 f1f0 f1 e0e1e0e1 b Total faults = 12 Structural Equivalence collapsed faults = 8 Structural Dominance collapsed faults = 6 Three tests, {00,01,10}, cover all faults

7. Aug. 8, 2007VDAT: Sandireddy & Agrawal7 Functional Collapsing Two faults are functionally equivalent if the corresponding faulty functions are identical. Functional dominance can be similarly defined. Determination of functional equivalence or dominance is as complex as test generation or equivalence checking. A graph-theoretic method for fault collapsing: –A. V. S. S. Prasad, V. D. Agrawal and M. V. Atre, “A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets,” Proc. Int. Test Conf., 2002, pp. 391-397. –V. D. Agrawal, A. V. S. S. Prasad and M. V. Atre, “Fault Collapsing via Functional Dominance,” Proc. Int. Test Conf., 2003, pp. 274-280.

8. Aug. 8, 2007VDAT: Sandireddy & Agrawal8 Dominance Collapsed Set a e c a 0 a 1 b0 b1b0 b1 c 0 c 1 d f d0 d1d0 d1 f 0 f 1 e0e1e0e1 b Total faults = 12 Structural Equivalence collapsed faults = 8 Structural Dominance collapsed faults = 6 Functional dominance collapsed faults = 4 Two tests, {01,10}, cover all faults

9. Aug. 8, 2007VDAT: Sandireddy & Agrawal9 Functional Collapsing: XOR Cell a b c d e g h i j k m c 0 c 1 d0d1d0d1 Functional dominance examples: d 0 → j 0, k 1 → g 0 f All faults = 24 Str. Equ. Faults = 16 Str. Dom. Faults = 13 Func. Dom. Faults = 4

10. Aug. 8, 2007VDAT: Sandireddy & Agrawal10 Hierarchical Fault Collapsing Create a library –For smaller (gate-level) circuits, exhaustive (functional) collapsing may be done. –For larger circuits, use structural collapsing. For hierarchical circuits, at any level of hierarchy, say n th level: –Read-in preprocessed (library) collapse data of (n-1) level sub-circuits. –Structurally collapse the interconnects and gate faults of n th level. -R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits,” Proc. Design, Automation and Test in Europe Conf., March 2005, pp. 1014–1019. -R. Hahn, R. Krieger, and B. Becker, “A Hierarchical Approach to Fault Collapsing,” Proc. European Design & Test Conf., 1994, pp. 171–176.

11. Aug. 8, 2007VDAT: Sandireddy & Agrawal11 A Fault Collapsing Library Cell name Cell characteristicsCollapsed fault set size Func. coll. CPU (s)* No. of inputs No. of outputs No. of gates Total faults StructuralFunctional EquDomEquDom Logic gates n112n+2n+2n+1n+2n+1- XOR2142416131047.9 HA2253020161569.1 FA3211603830261215.7 * Sun Ultrasparc 5_10 (360MHz, 128MB)

12. Aug. 8, 2007VDAT: Sandireddy & Agrawal12 Collapse Ratios for Ripple-Carry Adders Collapse ratio Total faults2341,85814,850 118,786 475,138 In hierarchical collapsing, faults in lowest level cells (XOR, full-adder, half-adder) are functionally collapsed. Programs used:1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 2. Fastest (obtained from Univ. of Wisconsin at Madison) 3. Our program (Auburn Univ.)

13. Aug. 8, 2007VDAT: Sandireddy & Agrawal13 CPU Time (sec) Improvement by Hierarchy for Ripple-Carry Adder

14. Aug. 8, 2007VDAT: Sandireddy & Agrawal14 Rent’s rule Rent’s Rule: Number of inputs and outputs terminals (T) for a typical block containing G logic gates is given by: T = K × G α α ~ 0.5 to 0.65 CPU time for collapsing a large hierarchical circuit is dominated by the time taken to build the structure of the circuit which is proportional to the T 2 (ref: our previous work). G is proportional to area

15. Aug. 8, 2007VDAT: Sandireddy & Agrawal15 Hierarchical 8-Bit Ripple Carry Adder Here α ~ 1.0, hence the total collapse time is quadratic in circuit size as observed in our experiment.

16. Aug. 8, 2007VDAT: Sandireddy & Agrawal16 Hierarchical Array Multiplier n/2×n/2 Additional Circuitry n × n multiplier prop. to √G n/2×n/2 Here α ~ 0.5, hence we expect the total collapse time to grow linearly with circuit size. Inputs prop. to √G Outputs

17. Aug. 8, 2007VDAT: Sandireddy & Agrawal17 Collapse Ratios for Array Multipliers Collapse ratio Total faults 84 726 3762 16,842 71,034 291,546 1,181,082 In hierarchical collapsing, faults in lowest level cells (XOR, full-adder, half-adder) are functionally collapsed. Programs used:1. Hitec (obtained from Univ. of Illinois at Urbana-Champaign) 2. Fastest (obtained from Univ. of Wisconsin at Madison) 3. Our program (Auburn Univ.)

18. Aug. 8, 2007VDAT: Sandireddy & Agrawal18 CPU Time Improvement by Hierarchy for Array Multipliers

19. Aug. 8, 2007VDAT: Sandireddy & Agrawal19 Conclusion Benefits of hierarchical fault collapsing: –Better (lower) collapse ratios due to functional collapsing of library cells. –Order of magnitude reduction in collapse time. Possible benefits of smaller fault sets: –Fewer test vectors –Efficient fault simulation –Easier fault diagnosis Further investigations: –Structural problems (testability measures, static timing analysis, physical design, etc.) may be solved using hierarchy. –Functional problems (ATPG, simulation, etc.) may require new hierarchical algorithms. Dom. Collapsed Set Size (Collapse Ratio) CPU s FlatHierarchicalFlatHier 53,4284 (0.45)26,5824 (0.23)2764540 128-bit multiplier