1. Dominance Fault Collapsing - Alok Doshi ELEC 7250 Spring 2004

2. Fault Collapsing The basic idea behind fault collapsing is to reduce the number of faults that have to be considered during the test generation process, in turn reducing the size of the test vector set. Fault collapsing eliminates those faults that can be detected by tests generated for some other faults.

3. Dominance Fault Collapsing If all tests of fault F1 detect another fault F2, then F2 is said to dominate F1. s-a-1 F1 s-a-1 F2 s-a-1 s-a-0 001 110 010 000 101 100 011 All tests of F2 Only test of F1

4. Structural Dominance Fault Collapsing Summarized as follows; An n–input Boolean gate requires n+1 single stuck at faults to be modelled. To collapse faults of a gate, all faults from output can be eliminated retaining one type (s-a-1 for AND and NAND; s-a-0 for OR and NOR) of fault on each input and the other type (s-a-0 for AND and NAND; s-a-1 for OR and NOR) on any one of the inputs. The output faults of the NOT gate, the non – inverting buffer, and the wire can be removed as long as both faults on the input are retained. No collapsing is possible for fanout. Also no collapsing is possible for the XOR and XNOR gates.

5. Algorithm 1. Read the bench file and convert it to a format easy to access. 2. Now read this file and take all data into the structure. Check for errors made in the bench file. 3. Find all fanouts of a gate. 4. Find all primary inputs with fanouts. 5. Find primary inputs without fanouts and whose output feeds into a gate which has all its inputs as primary inputs without fanouts. 6. Find all gates into which the primary inputs with fanouts feed. 7. Find all gates which are fanouts of other gates. (These should not include the gates that have any of its input as a primary input). 8. Calculate collapse ratio.

6. Example 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15

7. Example 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15

8. Example 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15

9. Example 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15

10. Example 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15

11. Results C17ALU(XOR)ALU(NAND)Full Adder8-bit Adder Total Faults5453267680634 Equivalence collapsed faults 2223730138290 Dominance collapsed faults 1620824830226 Fault Coverage (Equivalence) 1-0.973411 Fault Coverage (Dominance) 1-0.967711 Collapse Ratio (Equivalence) 0.4070.44520.4750.457 Collapse Ratio (Dominance) 0.2960.3660.3900.3750.356 # of Vectors (Equivalence) 10-36820 # of Vectors (Dominance) 10-48816

12. Redundant faults in ALU(NAND) Equivalence Dominance 86 2 1 ---------- 74 1 0 58 1 1 88 2 1 ---------- 77 1 0 63 1 1 90 2 1 ---------- 80 1 0 67 1 1 92 2 1 ---------- 83 1 0 70 1 1