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Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud.

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Presentation on theme: "Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud."— Presentation transcript:

1 Independence Fault Collapsing and Concurrent Test Generation Thesis Advisor: Vishwani D. Agrawal Committee Members: Victor P. Nelson, Charles E. Stroud Dept. of ECE, Auburn University January 25, 2006 Master’s Defense Alok S. Doshi Dept. of ECE, Auburn University

2 Jan. 25, 2006Alok Doshi: MS Defense2 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

3 Jan. 25, 2006Alok Doshi: MS Defense3 Problem Statement To find a minimal test vector set to detect all single stuck-at faults in a combinational circuit.

4 Jan. 25, 2006Alok Doshi: MS Defense4 Motivation ATPGTests Hitec 1 10 Fastest 2 7 Gentest 3 7 Atalanta 4 6-9 1 T. M. Niermann and J. H. Patel, “HITEC: A Test Generation Package for Sequential Circuits,” Proc. European Design Automation Conference, Feb. 1991, pp. 214-218. 2 T. P. Kelsey, K. K. Saluja, and S. Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. Computers, vol. 42, no. 11, pp. 1361-1371, Nov. 1993. 3 W. T. Cheng and T. J. Chakraborty, “Gentest: An Automatic Test Generation System for Sequential Circuits,” Computer, vol. 22, no. 4, pp. 43–49, April 1989. 4 H. K. Lee and D. S. Ha, “Atalanta: An Efficient ATPG for Combinational Circuits,” Tech. Report 93-12, Dept. of Electrical Eng., Virginia Poly. Inst. and State Univ., Blacksburg, Virginia, 1993. C17 - ISCAS85 Benchmark Circuit a b c d e x y Minimum4

5 Jan. 25, 2006Alok Doshi: MS Defense5 Motivation 4-bit ALU (74181) ATPGTests Gentest42 Fastest37 Hitec36 Atalanta23-39 Minimum12

6 Jan. 25, 2006Alok Doshi: MS Defense6 Background v1v1 v2v2 v3v3... T(F1) T(F2) Problem of finding a minimal test: Static compaction cannot guarantee optimality. Dynamic compaction is complex. Solution: Target both faults F1 and F2 at the same time to find a single test. Test set for fault F1 Test set for fault F2

7 Jan. 25, 2006Alok Doshi: MS Defense7 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

8 Jan. 25, 2006Alok Doshi: MS Defense8 Fault Classification F1 and F2 are equivalent. F1 dominates F2. F1 and F2 are independent. F1 and F2 are concurrently testable. T(F1) = T(F2) T(F1) T(F2) T(F1) T(F2) T(F1)

9 Jan. 25, 2006Alok Doshi: MS Defense9 Definitions Independent Faults 5 : Two faults are independent if and only if they cannot be detected by the same test vector. Concurrently-Testable Faults: Two faults that neither have a dominance relationship nor are independent, are defined as concurrently-testable faults. 5 S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the role of Independent Fault Sets in the Generation of Minimal Test Sets,” in Proc. International Test Conf., 1987, pp. 1100-1107.

10 Jan. 25, 2006Alok Doshi: MS Defense10 Structural Independences sa1 sa0 sa1

11 Jan. 25, 2006Alok Doshi: MS Defense11 Implied Independences Equivalence implied independence: If two faults are equivalent then all faults that are independent of one fault are also independent of the other fault. Dominance implied independence: If one fault dominates a second fault then all faults that are independent of the first fault are also independent of the second fault.

12 Jan. 25, 2006Alok Doshi: MS Defense12 Functional Independences

13 Jan. 25, 2006Alok Doshi: MS Defense13 Example Circuit 2-1 4-1 1-1 6-1 8-1 7-1 3-1 9-1 5-1 10-1 11-1 a b c d e x y C17 - ISCAS85 Benchmark Circuit 6 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019.

14 Jan. 25, 2006Alok Doshi: MS Defense14 Independence Matrix and Graph C17 - ISCAS85 Benchmark Circuit F1234567891011 101111100101 210011010001 310001111011 411001010001 511110001110 610100011100 701110101100 800101110111 910001111011 1000101001101 1111110001110

15 Jan. 25, 2006Alok Doshi: MS Defense15 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

16 Jan. 25, 2006Alok Doshi: MS Defense16 Independence Fault Collapsing The aim of independence fault collapsing is to collapse the independence graph into a fully- connected graph such that all or most faults in a given node will have a single test. These nodes will then serve as fault targets for Automatic Test Pattern Generation (ATPG).

17 Jan. 25, 2006Alok Doshi: MS Defense17 Cliques

18 Jan. 25, 2006Alok Doshi: MS Defense18 Clique A clique is defined as a fully-connected subgraph, i.e., a subgraph in which every node is connected to every other node. A lower bound on the number of tests required to cover all faults of an irredundant combinational circuit is given by the size of the largest clique of the independence graph.

19 Jan. 25, 2006Alok Doshi: MS Defense19 Degree of Independence Degree of Independence: This is the number of edges attached to the fault node and is computed for the i th fault by adding all the elements of either the i th row or the i th column of the independence matrix. DI (i th fault) = Σ x ij = Σ x ji NN j=1i=1

20 Jan. 25, 2006Alok Doshi: MS Defense20 Degree of Independence Fault1234567891011DI 1011111001017 2100110100015 3100011110117 4110010100015 5111100011107 6101000111005 7011101011006 8001011101117 9100011110117 10001010011015 11111100011107 DI75757567757

21 Jan. 25, 2006Alok Doshi: MS Defense21 Similarity Metric Similarity Metric: This is a measure defined for a pair of faults that determines how similar they are in their independence and concurrent-testability with respect to the entire fault set of the circuit. SIM (fault-i, fault-j) = Nx ij + (1-x ij ) Σ |x ik -x jk | N k=1

22 Jan. 25, 2006Alok Doshi: MS Defense22 Similarity Metrics Fault1234567891011 10 34 4 2 04 6 646 3 404 0 4 40 6 646 5 043 0 6 6 640 44 73 3 0 53 846 6 0 9 404 0 1046116 45 0 043 0

23 Jan. 25, 2006Alok Doshi: MS Defense23 Similarity Metric of a Fault-Pair Highly Dissimilar Highly Similar EquivalentIndependent (Group together)(Group separately) Similarity metric of a fault-pair Max. 0

24 Jan. 25, 2006Alok Doshi: MS Defense24 Step 1 – Compute Degree of Independence (DI) for All Faults Fault1234567891011DI 1011111001017 2100110100015 3100011110117 4110010100015 5111100011107 6101000111005 7011101011006 8001011101117 9100011110117 10001010011015 11111100011107 DI75757567757

25 Jan. 25, 2006Alok Doshi: MS Defense25 Step 2 – Order Faults by DI Fault1358911724610DI 1011011011107 3101101100117 5110110011017 8011011100117 9101101100117 11110110011017 7010110011106 2101001101005 4101001110005 6110110100005 10011111000005 DI77777765555

26 Jan. 25, 2006Alok Doshi: MS Defense26 Step 3 – Compute Similarity Metrics for All Fault-Pairs 1 3 51,8 3,9 5,115,11,7 3,9,244,64,6,10 11 4 0 03 4 6 F13589 724610 1011 4 3 4 3 0 0 44 5 0 03 4 84 0 66 9 0 0 44 0 03 4 73 3 30 5 2 4 64 0 66 4 4 64 066 6 4 4 6604 10411 56640 Similarity index for fault F for each existing node i: Max. SIM (F, k th fault of node i) where k = 1…..K, and K is number of faults in node i. Step 4 – Collapse the Graph

27 Jan. 25, 2006Alok Doshi: MS Defense27 Bounds on Number of Tests N c < Number of tests < Σ where, N c ’ is the number of nodes in the collapsed graph (N c ’ ≥ N c ). and, k i is the number of faults in the i th node. For C17, 4 < Number of tests < 7. Nc’Nc’ i=1 kiki 2 _

28 Jan. 25, 2006Alok Doshi: MS Defense28 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

29 Jan. 25, 2006Alok Doshi: MS Defense29 Concurrent Test Generation Concurrent Test: Given a set of target faults, a concurrent-test is an input vector that detects all (or most) faults in the set.

30 Jan. 25, 2006Alok Doshi: MS Defense30 Concurrent D Algebra for 2-Input AND Gate

31 Jan. 25, 2006Alok Doshi: MS Defense31 Concurrent Test Generation for C17 2-1 3-1 9-1 0 1 1 1 1 D2D2 D2D2 D3D3 D9D9 D3D3 D9D9 D 23 D 39 0

32 Jan. 25, 2006Alok Doshi: MS Defense32 Concurrent Test Generation for C17 Fault TargetsTest (a b c d e) 1,810010 3,9,201111 5,11,7X1010 4,6,1010101 2-1 4-1 1-1 6-1 8-1 7-1 3-1 9-1 5-1 10-1 11-1 a b c d e x y

33 Jan. 25, 2006Alok Doshi: MS Defense33 Results (ALU – 74181) NodeNumber of faultsTest vectors no.TotalTargetedDetected fromCumulative this node other nodes coverage 155561101001111010001 233321601001111110101 387732601011101000001 4333332101x0101010000 553343910100101011000 666624711111000001001 774435411100000100000 81411 16611100110101011 986517210010100110101 108432771x101011101100 1183318101010000101100 129221841x011110001100

34 Jan. 25, 2006Alok Doshi: MS Defense34 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

35 Jan. 25, 2006Alok Doshi: MS Defense35 Simulation-Based Techniques The functional dominance fault collapsing 6, used prior to independence fault collapsing, is based on ATPG and is complex. The independence graph generation procedure is also based on ATPG. The use of concurrent D-algebra requires a new ATPG program that may not be readily available to a user. 6 R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and Detection Fault Collapsing for Multiple Output Circuits," in Proc. Design, Automation and Test in Europe (DATE) Conf., Mar. 2005, pp. 1014 - 1019.

36 Jan. 25, 2006Alok Doshi: MS Defense36 Simulation-Based Independence Fault Collapsing Start with a fully-connected independence graph for an equivalence collapsed fault set (structural collapsing only), i.e., assume initially all faults are independent of each other. Simulate random vectors without fault dropping to remove edges between faults detected by the same vector. Stop the random vector simulation when a large number of vectors do not remove any new edges. Apply the original independence fault collapsing algorithm on the generated independence matrix.

37 Jan. 25, 2006Alok Doshi: MS Defense37 Simulation-Based Independence Fault Collapsing 74181 4-bit ALU 301

38 Jan. 25, 2006Alok Doshi: MS Defense38 Simulation-Based Concurrent Test Generation For each group, generate all test vectors for the first fault in the group. –If the number of test vectors for a fault is large, use a subset (e.g., 250 maximum) of vectors. Simulate all faults in the group to select one vector that detects most faults in that group. –If more vectors than one detect the same number of faults within the group, then select the vector that detects most faults outside the group as well.

39 Jan. 25, 2006Alok Doshi: MS Defense39 74181 4-Bit ALU Result Group numberNumber of faults in groupConcurrent test vector 1 2 3 4 5 6 7 8 9 10 11 12 13 9 15 11 6 11 17 11 16 22 56 81 01100011111100 01101100000110 10100101111010 11011010100000 10110101011010 10100111101010 10010101001110 01000111101011 11100010010011 11011100110100 01010001100001 All 56 faults detected by eleven previously generated vectors 10101001110110

40 Jan. 25, 2006Alok Doshi: MS Defense40 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

41 Jan. 25, 2006Alok Doshi: MS Defense41 * Sun Ultra 5 *** Pentium Pro PC ** Hamzaoglu and Patel, IEEE-TCAD, 2000 Concurrent ATPG Results Circuit No. of concurrent groups Concurrent ATPG Single-fault ATPG VectorsCPU s* AtalantaBest known VectorsCPU s*VectorsCPU s*** 1-b adder 2-b adder 4-b adder 8-b adder 16-b adder 32-b adder 4-b ALU c17 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 5 7 13 4 30 52 24 84 106 81 107 92 23 190 5 7 9 11 12 4 34 52 29 84 111 92 130 104 25 198 0.085 0.092 0.103 0.182 3.3 9.7 11.4 0.082 10.4 14.6 23.3 34 49.6 57.6 119.6 216.3 158.1 360.7 5-7 7-9 8-11 10-15 13-22 17-25 22-40 6-9 49-77 54-68 52-106 85-109 118-173 106-192 147-263 114-224 32-48 209-358 0 0.017 0.050 0.033 0 0.083 0.033 0.133 0.1 0.5 1.2 1.9 0.733 4.7 5.283 5 12 4 27** 52** 16** 84** 106** 44** 84** 37** 12** 73** - 15 0.1 21.9 0.9 88.1 47.1 174.5 748.6 347.7 663.8

42 Jan. 25, 2006Alok Doshi: MS Defense42 Number of Vectors for Increasing Circuit Sizes (100% Stuck-at Coverage) Single-fault ATPG (no compaction) Concurrent ATPG Minimum achieved! (dynamic compaction) 1-bitc7552 adder

43 Jan. 25, 2006Alok Doshi: MS Defense43 CPU Seconds for Increasing Circuit Sizes (100% Stuck-at Fault Coverage) Concurrent ATPG Minimum achieved! (dynamic compaction) 1-bitc7552 adder

44 Jan. 25, 2006Alok Doshi: MS Defense44 Outline Introduction –Problem Statement –Motivation –Background Contributions of this Research –Fault Classification and Independent Faults –Independence Fault Collapsing –Concurrent Test Generation –Simulation Based Techniques –Results Conclusions and Future Work

45 Jan. 25, 2006Alok Doshi: MS Defense45 Conclusions Concurrent test generation produces compact tests when combined with independence fault collapsing. ATPG and set covering problems have exponential time complexities. Hence, we cannot expect absolute optimality for large circuits. The concurrent ATPG procedure gives significantly smaller, and sometimes the optimum, test sets.

46 Jan. 25, 2006Alok Doshi: MS Defense46 Future Work There is scope for improving the simulation- based algorithms for independence fault collapsing and concurrent test generation. –Can be made more dynamic. Concern about memory requirement. Implement an ATPG program using the concurrent D algebra.

47 Jan. 25, 2006Alok Doshi: MS Defense47 Future Work – Another Collapsing Technique 6 8 7 6, 5 8, 4 7, 1 6, 5, 11 7, 1, 10 9 9, 3 9, 3, 2 11 4 0 3 4 F13589 724610 1011 4 3 4 3 0 0 44 5 0 03 4 84 0 66 9 0 0 44 0 03 4 73 3 30 5 2 4 64 0 66 4 4 64 066 6 4 4 6604 10411 56640 Fault Targets Test (a b c d e) 6, 5, 1101100 7, 1, 1010011 8, 410100 9, 3, 201111 11 4 6 5

48 Jan. 25, 2006Alok Doshi: MS Defense48 Thank You!


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