Xilinx CPLD Software Solutions The Foundation Series shrink-wrapped, single point solution containing schematic entry, HDL (VHDL, Verilog & ABEL) and simulation capabilities as well as our FPGA and CPLD implementation technologies. PC based, Windows 95 & Windows NT The Alliance Series FPGA and CPLD implementation technologies and interfaces for our 3rd party alliance partners. Synopsys, Exemplar, Synplicity, Model Technology, Mentor Graphics, Cadence, Aldec, Orcad, Viewlogic, etc.. PC & Workstation based (Windows 95, 98, NT v4.0, Solaris, HP & RS6000) This CPLD implementation technology is included in every software package that Xilinx offers! Whether you choose Foundation or Alliance OR Base or Standard, the customer can utilize all these technological advantages. Foundation Series software is a complete ready-to-use set of tightly integrated, easy-to-use tools that give you the highest performance and the highest density FPGA and CPLD implementations, independent of your expertise or the complexity of your design. Foundation incorporates schematic entry, gate-level simulation and a suite of HDL based tools that allow customers to use industry standard languages, like VHDL, Verilog and ABEL. The Foundation Series tool suite is available on PC based platforms supporting Windows 95 and Windows NT 4.0. The Alliance Series software provides a complete set of powerful, fully integrated development tools that work seamlessly within your chosen EDA environment. While Xilinx supplies the interface and libraries to work with the Cadence, Mentor and Synopsys (including Viewlogic), Xilinx is committed to enhancing the integration with amny more of our Alliance Partners, like Synplicity, Exemplar, Aldec, Model Technology, etc...

Xilinx Foundation Series Ready To Use Design Solutions The Xilinx Foundation Series provides it’s users with a ready to use design solution. Focused on providing a superior HDL based design solution while maintaining a high degree of ease-of-use for the first time user. A combination of intuitive GUIs, design wizards and push button flows gives the first time user a quick and efficient implementation of his/her design. Coupled with this is a superior HDL solution. The Foundation Series utilizes the Synopsys FPGA Express synthesis technology as the underlying engine which allows full support of VHDL and Verilog. By using the color coded & graphical HDL editor, in conjunction with HDL design wizards, makes designing VHDL, Verilog and ABEL designs quick and efficient. Intuitive GUIs & Design Wizards Mixed-Level Design Environment Push-Button Design Flows Comprehensive Help/Tutorials Synopsys FPGA Express technology VHDL, Verilog & ABEL HDL support Graphical HDL & Constraint Entry Performance Driven Synthesis

Xilinx CPLD Implementation Flow Simplified Project Management Implementation Templates for Speed & Density Push Button Design Flows Whether you choose the Foundation Series or the Alliance Series, Xilinx offers an easy-to-use implementation flow for CPLD designs. With simplified, easy to understand project management coupled with intuitive push button flows, a CPLD designer can navigate their design from netlist entry to JEDEC programming file in minutes. Pre-defined implementation templates allow the user to quickly target, or retarget, their design to best fit their current objectives. Continuing enhancements in both fitting technology algorithms and compile time directives give designers faster system clock speeds, faster compile times, higher device utilization and maintains the industry’s best pin-locking solution! Performance algorithm enhancements ensure faster clock speeds,higher device utilization and the industry’s best pin-locking capabilities!

JTAG based In System Programming IEEE 1149.1 Industry Standard programs both CPLDs and FPGAs XC9500 (M1.4) XC9500XL, XC4000E/X (M1.5) SPARTAN/XL, VIRTEX (M1.5) automatic device recognition via ‘IDCODE’ concurrent CPLD device programming Embedded vector support for ‘INTEST’ supports ‘JTAG’ parallel & ‘XChecker’ serial download cables supports all platforms Xilinx CPLDs use the industry standard IEEE 1149.1 JTAG programming interface to download into its’ devices. By fully supporting IEEE 1149.1, customers can take advantage of the unique capabilities of JTAG like ‘IDCODE’ and ‘INTEST’. All of the features detailed above are fully integrated into the tool, with the newest being the support for FPGA device programming (M1.5). Xilinx has made major enhancements to it’s JTAG programming software over the last release and will continue that tradition into the future.

XC9500 CPLDs for COREs Implementations High system clock speeds (Fcyc) fastest pin-to-pin delays (Tpd) non-volatile, FLASH based ISP Utility Chip enhancement / replacement Applications (Utility Chips / Fix) DMA Controllers DRAM Controllers PCI Arbitration UARTs, Peripheral Interface Controllers, etc... Industry leading pin-locking technology ensures quick, efficient and predictable results LogiBLOX (M1.5) & CORE Generator M2.1 support Xilinx, as a corporation, is committed to be the leader in CORE’s and CORE technology software. Xilinx CPLDs augment that strategy by offering features such as: superior system clock speeds fast pin-to-pin delays non volatility re-programmability via JTAG CPLD specific COREs can used in a variety of ways; discontinued logic replacement, logic enhancement or logic consolidation. By taking advantage of the In System Programmability feature of the FLASH based CPLD architecture, designers can speed up their design or provide field update capability to support emerging standards. In the M1.5 release, the XC9500 & XC9500XL will be fully supported by LogiBLOX. In the M2.1 release, CPLD specific additions and enhancements will be included in the Core Generator.

CPLD Implementation Tools Roadmap Multi-Level Logic Re-Timing Optimization Enhanced LogiCORE & COREGen specific CPLD support HDL Centric Design & Simulation Flows CPLD Design Viewer ISP Manager & Cable 98 Added JTAG Programmer support for new IC families Embedded Foundation HDL Testbench into JTAG Debugger GUI Re-Design ‘Ease-of-Use’ Focus - Phase III M2.1 Features / Enhancements Automatic Logic Decomposition Look-Ahead P-Term Collapsing LogiBLOX and AllianceCORE specific CPLD support HDL Centric Design Flows Constraints Editor support Added JTAG Programmer Support for XC9500XL & FPGAs GUI Re-Design ‘Ease-of-Use’ Focus - Phase II M1.5 Multi-Level Logic Synthesis Dynamic Macrocell Utilization Pre-Defined Implementation Templates XC9500 JTAG Programmer Support Embedded ABEL Test Vector Support in JTAG Programmer GUI Re-Design ‘Ease-of-Use’ Focus - Phase I M1.4 The CPLD specific Implementations tools roadmap shows: the major feature enhancements included in the M1.4 release the specifics of what will be contained in the M1.5 release what is planned for the M2.1 release Both Alliance 1.4 and Foundation 1.4 are available today! M1.5 will be shipping to Alliance customers in early August 1998 M1.5 will be shipping to Foundation customers one month later Alliance 2.1 is planned for release at the end of the 1st calendar quarter of 1999. Foundation 2.1 will follow approximately one month later. M1.4 M1.5 M2.1 1998 1999

Xilinx Foundation & Alliance Series Platform & Device Support 1.4 1.5 PC Platform 2.1 Windows 95 (Japanese, Chinese & Korean) Windows NT 4.0 NEC PC98* Windows 95 (Japanese, Chinese & Korean) Windows NT 4.0 NEC PC98* Windows 95 & 98 (Japanese, Chinese & Korean) Windows NT 4.0 NEC PC98* IBM PC or compatible XC3x00A/L XC5200 XC4000E/X Spartan XC9500 XC3x00A/L XC5200, Spartan/XL XC4000E/X XC9500/XL Virtex plus Next Generation IC families Workstation SunOs Solaris HP-UX RS6000 CDE (4.1.3 tactical) & 4.1.4 2.5 10.2 AIX 4.1.5 (FPGA only) yes Not Supported 2.5 & 2.6 10.2 AIX 4.1.5 yes Not Supported 2.5 & 2.6 10.2 AIX 4.1.5 yes This is an overview of the Xilinx platform and device support for the M1.4, M1.5 and M2.1 software releases. As well as continuing to support the major platforms and current operating systems, Xilinx is committed to supporting the localized version of Japanese, Chinese and Korean Windows on the PC as well as CDE support for the workstation. 1.4 1.5 2.1 * NEC PC98 is available for Alliance Platforms only

CPLD M1.4 Software Roadmap Features & Device Support Implementation Technology CPLD Quick Install re-design (simplification) of GUI options pre-defined Implementation Templates improved support of constraints dynamic macrocell utilization multi level optimization (use of OPTX) by default (10-15% density/speed improvement) JTAG Programmer concurrent programming (speeds up program & erase) auto device recognition using ‘IDCODE’ basic TAP debug embedded ABEL test vector support for ‘INEST’ Status Alliance 1.4 & Foundation 1.4 available now! Xilinx CPLD implementation technology made several enhancements in the M1.4 release. Most notably: pre-defined implementation templates for density and speed CPLD quick install improved timing constraints support dynamic macrocell utilization based on timing constraints default use of multi level logic optimization to reduce overall design density and increase performance The JTAG programming software added a few key features as well: automatic device identification within the JTAG chain using ‘IDCODE’ speeding up parallel programming with a concurrent program feature support of the ‘INTEST’ command with embedded ABEL vectors Alliance 1.4 and Foundation 1.4 are available and shipping today!

CPLD M1.5 Software Roadmap Features & Device Support Implementation Technology automatic timing and density logic decomposition look-ahead pterm collapsing (optimal speed & density) CPLDs now support LogiBLOX module synthesis new AllianceCORE CPLD based Intellectual Property Founadtion focus on HDL-centric entry/verification CPLD support within Xilinx Constraints Editor JTAG Programmer new device support: 9500XL, 4000E/X, 5200 & SPARTAN/XL VIRTEX support added in an interim release Status Alliance 1.5 available August ‘98 Foundation 1.5 available September ‘98 The M1.5 release of Alliance and Foundation are key releases in our continuing efforts towards ‘ease-of-use’. These features include the the introduction of the graphical Constraints Editor for both Foundation and Alliance users. From a Foundation specific viewpoint, both the Implementation and Synthesis tools are now fully integrated. This is a major leap forward in addressing both ease-of-use and improved first time users experience. CPLD specific advancements include: automatic timing & density logic decomposition based on timing constraints. Improved density and runtimes with the use of look-ahead product term collapsing. Full LogiBLOX support of the XC9500/XL families. XC9500/XL support in the graphical constraints editor Also, with this release, the JTAG programming software now supports the XC4000E/X, XC5200 & SPARTAN/XL FPGA families. The VIRTEX FPGA family will be supported in an interim release prior to the M2.1 release.

CPLD M2.1 Software Roadmap Features & Device Support Implementation Technology Multi-Level Logic Re-Timing Optimization Enhanced LogiCORE & COREGen specific CPLD support HDL Centric design & simulation flows CPLD Design Viewer JTAG Programmer Embedded Foundation HDL testbench support in JTAG Programmer Cable 98 support ISP manager new FPGA device support Status Alliance & Foundation 2.1 available 1Q99 With the M2.1 release, the following features are planned: multi-level logic re-timing allows the software to reoptimize a design based on specified timing requirements. XC9500/XL integration into the COREGen tool suite. Added designs form both 3rd party vendors and Xilinx resources into the AllianceCORE program. CPLD specific design viewer / ‘floorplanner’ for design analysis and graphical constraint entry. A strong focus on ‘plug & play’ HDL integration for 3rd party HDL synthesis and simulation tools. The JTAG programmer will be enhanced to support: Embedded HDL testbench vectors fro use with the ‘INTEST’ JTAG command. Introduction of an ISP manager, for Alliance based flows, to allow control and portability of programming files across multiple programming tools and multiple platforms. The M2.1 release is scheduled to ship in the 1st half of 1999.