1. Course Agenda
DSP Design Flow

2. Schedule Start @ 9am Break @ 10:30am Lunch @ noon Break @ 3:00pm
5pm

3. Objectives After completing this course, you will be able to:
Describe the different design flows for implementing DSP functions, with a large focus on the System Generator
Understand the Xilinx FPGA capabilities and know how to implement a design from algorithm concept to hardware simulation
Perform Hardware in the Loop targeting the Digilent Spartan-3 board

4. Day 1 Introduction DSP Design Flows in FPGA Power of Parallelism
Platform FPGA Virtex-II/ Virtex-II Pro Series
Spartan-3 Architecture
DSP Design Flows in FPGA
Using VHDL
Using the Xilinx CORE Generator
Using the Xilinx System Generator for DSP
Hardware in the Loop Accelerated Verification
System Generator 3.1 introduces two additional modes of simulation support:
HDL Co-Simulation (next slide)
Hardware in the Loop accelerated simulation
With System Generator 3.1, the designer can connect the real hardware to Simulink simulator through Parallel Cable IV, USB, or PCI. User can generate hardware platform specific configuration file, and then simulate the design from Simulink environment.

5. Day 2 Digital Filtering Controlling the System Multi-Rate Systems
Digital Filtering Blocks
Use the FDA Tool in Conjunction with the Xilinx Blockset
Controlling the System
Control functions
Multi-Rate Systems
Clocking scheme
Hardware point of view
HDL Co-simulation supported by System Generator 3.1 allows designers to incorporate HDL code as part of overall design and simulate it using ModelSim simulator.
Day 2 continued on next page.

6. Day 2 Looking Under the Hood Controlling the System Multi-rate Systems
Quantization and Overflow
Hardware Cost
Data Path Management
Controlling the System
Control Mechanism
Control Blocks
Multi-rate Systems
Sample Rates
Sample Rate Changing Blocks
Hardware Realization of Sample Rate Changing Blocks
HDL Co-simulation supported by System Generator 3.1 allows designers to incorporate HDL code as part of overall design and simulate it using ModelSim simulator.