HIGH LEVEL SYNTHESIS.

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Presentation transcript:

HIGH LEVEL SYNTHESIS

Digital Circuits General-purpose processors: High-volume sales. High performance. Application-Specific Integrated Circuits (ASICs): Varying volumes and performances. Large market share. Special applications (e.g. space).

Computer-Aided Design Enabling design methodology. Makes electronic design possible: Large scale design management. Design optimization. Feasible implementation choices grow rapidly with circuit size Reduced design time. CAD tools have reached good level of maturity. Continuous grows in circuit size and advances in technology requires CAD tools with increased capability. CAD tools affected by Semiconductor technology Circuit type

Digital System Design Styles Adapt circuit design style to market requirements Parameters: Cost. Performance. Volume. Full custom Maximal freedom High performance blocks Slow Semi-custom Standard Cells Gate Arrays Mask Programmable (MPGAs) Field Programmable (FPGAs)) Silicon Compilers & Parametrizable Modules (adder, multiplier, memories)

Semi-Custom Design Styles

How to Deal with Design Complexity? Moore’s Law: Number of transistors that can be packed on a chip doubles every 18 months while the price stays the same. Hierarchy: structure of a design at different levels of description Abstraction: hiding the lower level details.

Design Hierarchy Top – Down Bottom UP

Abstractions An Abstraction is a simplified model of some Entity which hides certain amount of the Internal details of this Entity Lower Level abstractions give more details of the modeled Entity. Several levels of abstractions (details) are commonly used: System Level Chip Level Register Level Gate Level Circuit (Transistor) Level Layout (Geometric) Level More Details (Less Abstract)

Design Domains & Levels of Abstraction Designs can be expressed / viewed in one of three possible domains Behavioral Domain (Behavioral View) Structural/Component Domain (Structural View) Physical Domain (Physical View) A design modeled in a given domain can be represented at several levels of abstraction (Details)

Three Abstraction Levels of Circuit Representation Architectural level: Operations implemented by resources. Logic level: Logic functions implemented by gates. Geometrical level: devices are geometrical objects.

Modeling Views Behavioral view: Structural view: Physical view: Abstract function. Structural view: An interconnection of parts. Physical view: Physical objects with size and positions.

Levels of Abstractions & Corresponding Views

Gajski and Kuhn's Y Chart

Design Domains & Levels of Abstraction

Design vs. Synthesis Design: Synthesis: A Sequence of synthesis steps down to a level of abstraction which is manufacturability Synthesis: Process of transforming H/W from one level of abstraction to a lower one Synthesis may occur at many different levels of abstraction Behavioral or High-level synthesis Logic synthesis Layout synthesis

Digital System Design Cycle Design Idea  System Specification Behavioral (Functional) Design Pseudo Code, Flow Charts Architecture Design Bus & Register Structure Logic Design Netlist (Gate & Wire Lists) Circuit Design Transistor List Physical Design VLSI / PCB Layout Fabrication & Packaging

Synthesis Process

Circuit Synthesis Architectural-level synthesis: Determine the macroscopic structure: Interconnection of major building blocks. Logic-level synthesis: Determine the microscopic structure: Interconnection of logic gates. Geometrical-level synthesis: (Physical design): placement and routing Determine positions and connections.

Architecture Design

Behavioral or High-Level Synthesis The automatic generation of data path and control unit is known as high-level synthesis. Tasks involved in HLS are scheduling and allocation Scheduling distributes the execution of operations throughout time steps Allocation assigns hardware to operations and values. Allocation of hardware cells include functional unit allocation, register allocation and bus allocation. Allocation determines the interconnections required.

Behavioral Description and its Control Data Flow Graph (CDFG) X = W + ( S * T ) Y = ( S * T ) + ( U * V ) * + W S T U V X Y (a) CDFG (b) W S T U V X Y 1 2 3 (c) Scheduled CDFG

Resulting Architecture Design MUX X Y W + Z * S U T V Bus 1 Data Path

Design Automation & CAD Tools Design Entry (Description) Tools Schematic Capture Hardware Description Language (HDL) Simulation (Design Verification) Tools Simulators (Logic level, Transistor Level, High Level Language “HLL”) Synthesis Tools Formal Verification Tools Test Vector Generation Tools