Dr. Clincy Professor of CS CS 3501 - Chapter 3 (3A and 10.2.2) Dr. Clincy Professor of CS Dr. Clincy Lecture Slide 1 1

Sequential Circuits Vs Combinational Circuits Sequential Logic Current State or output of the device is affected by the previous states Circuit Flip Flops New Input Previous State or Output Current State or Output Combinatorial or Combinational Logic Circuit New Input Current State or Output Current State or output of the device is only affected by the current inputs Dr. Clincy Lecture

Clock - Sequential Circuits State changes are controlled by clocks (clock ticks). Circuits can change state on the rising edge, falling edge, or when the clock pulse reaches its highest voltage – edge triggered. Level-triggered circuits change state when the clock voltage reaches its highest or lowest level. Dr. Clincy Lecture

Flip Flops - Sequential Circuits New Input Previous State or Output Current State or Output Notice how the output feeds the input Think of: Given R=0 and Qa=0, what can this be ? S and R stand for set and reset respectively constructed from a pair of cross-coupled NOR gates the stored bit is present on the output marked Qa If S and R inputs are both low, maintains the Qa and Qb in constant state, If S (Set) is pulsed high while R is held low, then the Qa output is forced high,and stays high even after S returns low; if R (Reset) is pulsed high while S is held low, then the Qa output is forced low, and stays low even after R returns low. Dr. Clincy Lecture

Gated SR Latch or Flip Flop The time at which the latch is SET or RESET is controlled by a CLOCK input Called Gated SR Latch Dr. Clincy Lecture

Gated D Latch Inputs S and R are derived from a single input D Clock pulse controls when the output is triggered Samples the D input at the time the clock is HIGH and stores that info until the next clock pulse During the time the clock is high, the input changed, causing the output to change – this is the problem Dr. Clincy Lecture

Potential Problem Thus far, the assumption has been the inputs S and R (or D) not changing while CLK is HIGH What would happen if S, R and/or D changed ? The output would change immediately This could be a problem To fix this (next ppt) During the time the clock is high, the input changed, causing the output to change – this is the problem Dr. Clincy Lecture

Two Flip Flop Use To Fix Clock Issue FF1 FF2 Q Q D D Q m D Q s Q Clock Clk Q Clk Q Q Use 2 D flip flops – the FF2 clock is set to zero – therefore, if there was a change in FF1 input, D, it wouldn’t effect the FF2 Q value – FF2 holds the value (a) Circuit Clock D Q m Q = Q s Clock’s negative edge causes change (b) Timing diagram If D changes while FF1 CLK is HIGH, Qm changes immediately - Qs stays the same because FF2 CLK=0 Once the CLK goes LOW, FF2 reacts because its CLK=1 – so it thens reflects D D Q The arrow only symbolizes “positive edge” clock - the arrow with the NOT symbolizes “negative edge” clock Q (c) Graphical symbol Dr. Clincy Lecture

Start Lab 6 Dr. Clincy Lecture Slide 9 9