1. Chapter 5
Sequential Circuits

2. Sequential Circuits Combinational Circuits + Storage element
output depends both on previous state and input
Fig. 5-1

3. Storage element (a): a buffer tG the delay
the information enters the buffer at t and output at t+ tG
the stored information only retained in buffer by tG
longer storage time is necessary in most applications
Fig. 5-2

4. Synchronous clocked sequential circuit
Use flip-flop
Fig. 5-3

5. 5-2 latch
A storage element can maintain a binary state indefinitely, until directed by an input signal to switch states.
The most basic storage elements are latches.
Fig. 5-4 SR latch with NOR gates

6. Simulation for SR latch
Fig. 5-5

7. - latch
Fig latch with NAND gates

8. - latch with control input
Fig. 5-7

9. D (Data) latch
Fig. 5-8

10. 5-3 Flip-Flops
A change in value on the control input allows the state of a latch in a flip-flop to switch.
This change is called a trigger
The trigger enable (trigger) the flip-flops
See Fig. 5-3 for sequential circuits
A present (original) and next (new) state occur in flip-flop before and after the trigger, respectively
The most important element in sequential circuits
Can be derived from latch

11. SR Master-Slave flip-flop
Fig. 5-9

12. Simulation for SR Master-Slave flip-flop
Pulse trigger
Pulse in the inputs SR will result wrong output
Fig. 5-10
Initially unknown
Unknown due to R=1 S=1
Pulse input results wrong output

13. Edge-trigger Flip-Flop
Negative-edge-trigger Flip-Flop
Fig. 5-11

14. Edge-trigger Flip-Flop
Positive -edge-trigger Flip-Flop

15. Symbols
Fig. 5-13

16. Symbols
Fig. 5-14

17. 5-4 Sequential Circuit Analysis
The output and the next state are a function of the inputs and the present state.
An example
input equations
output equation
Fig. 5-15

18. State table

19. Two-dimensional state table

20. Mealy model/Moore model
Mealy model circuits
Sequential circuits in which the outputs depend on the input, as well as on the states
The circuits in Fig. 5-15
Moore model circuits
Sequential circuits in which the outputs depend only on the states
The circuits in Fig. 5-16

21. A Moore model circuit (Fig. 5-16)

22. State diagram
(a): for Fig (b): for Fig. 5-16

23. Example 5-1 States reduction
equivalent

24. Example 5-1 States reduction

25. Example 5-1 States reduction
equivalent

26. Example 5-1 States reduction
Reduce from 4 states, 2 flip-flops to 2 states, 1 flip-flop
may or may not result in reduced cost

27. Sequential Circuit Simulation
A simulator for the input/output of a designed circuit
Functional simulation
Timing simulation