Felix Sefkow CALICE/EUDET electronics meeting CERN, July 12, 2007 2nd HCAL electronics Felix Sefkow CALICE/EUDET electronics meeting CERN, July 12, 2007

Few remarks on… SPIROC tests HCAL DIF Tile Hadron Calorimeter Felix Sefkow July 12, 2007

SPIROC test infrastructure LAL schedule: ASIC and test board available in October After SPIROC Delivery and first sanity checks Testboard software (LabView) Start with ‘slow control” (set parameters) Tools for control of digital part in parallel Question: data acquisition rates? Tests at DESY: 2 set-ups In: pulser, out: scope In: SiPM/MPPC, out: ADC/TDC (VME) Tile Hadron Calorimeter Felix Sefkow July 12, 2007

SPIROC tests Analogue part (with basic soft): Observables: shaped signals, trigger discri out, DAC voltages Preamp + shaper: Gain, noise, linearity (dynamic range), cross talk Trigger: threshold scan, time walk, jitter Both: impact of SiPM pulse shape variations DACs (trigger threshold and SiPM bias): linearity, dispersion Charge injection (level control?) No hold scan (sample and hold only via SCA  digital part) Digital part (as soft comes along): Hold scan, dispersion, effect of time walk and input shape variation ADC and TDC linearity (int, diff) Readout and trigger timing Memory management, multi-channel inputs Timing with SiPM: New feature Tile Hadron Calorimeter Felix Sefkow July 12, 2007

Technical prototype architecture ~ 2000 tiles/layer LDA (Module concentrator, Optical link) Very similar to SiW ECAL Following CALICE / EUDET DAQ concept SPIROC 2nd gen ASIC DIF (Layer Concentrator, Clock, control, Configuration) 2.2m With 40 µW / ch Temp gradient 0.3 K / 2m Layer units (assembly) subdivided into smaller PCBs HBUs:Typically 12*12 tiles, 4 ASICs Tile Hadron Calorimeter Felix Sefkow July 12, 2007

To LDA: data, CCC, slowC, diagnostics DIF architecture DIF board hosts: DIF proper: FPGA, LDA interface, fast signals, diagnostics i/f Calibration control power supply and slow control (e.g. temperature r/o) Connections: To HCAL layer: SPIROC data, CCC, power, slow control To other layers and LDA: data, CCC, power, s/c, diagnostics We consider (again) a baseboard + piggy back architecture Independent development, possibly initially separate boards To HCAL layer FPGA DIF CALIB P/S. S/C To LDA: data, CCC, slowC, diagnostics power Tile Hadron Calorimeter Felix Sefkow July 12, 2007

Interfaces, protocols Some are HCAL specific Some are generic Calibration to DIF, slowC to DIF SPIROC to DIF: benefits from test board s/w developments Some are generic DIF to LDA, including CCC should think about standardizing FPGA Should start to think about SlowC DIF could be separate board initially Evaluation board Prototype Where is optimal transition point from test board to DIF prototype? Tile Hadron Calorimeter Felix Sefkow July 12, 2007

Conclusion SPIROC tests: priority project at DESY in winter DIF: need standards to parallelize developments Tile Hadron Calorimeter Felix Sefkow July 12, 2007

Back-up slides Tile Hadron Calorimeter Felix Sefkow July 12, 2007

Integrated layer design Sector wall Reflector Foil 100µm Polyimide Foil PCB 800µm Bolt with inner M3 thread welded to bottom plate SiPM Tile 3mm HBU Interface 500µm gap Bottom Plate 600µm ASIC TQFP-100 1mm high Top Plate 600µm steel Component Area: 900µm high HBU height: 6.1mm (4.9mm without covers => absorber) Absorber Plates (steel) Spacer 1.7mm fixing DESY integrated Tile Hadron Calorimeter Felix Sefkow July 12, 2007

Alternative approach at NIU, Integrate sensor in PCB Schedule EUDET programme implies coherent schedule for technical prototypes Some milestones: ASICs: 1st proto in 2007, 2nd in 2008 DAQ: proto in 2008, system in 2009 Module: design in 2008, built in 2009 Started series of smaller test boards to validate design approach (DESY) LED integration ASIC integration Power system Alternative approach at NIU, Integrate sensor in PCB Tile Hadron Calorimeter Felix Sefkow July 12, 2007