A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS Good afternoon ,I’m Liu Wei from Tsinghua University. Today my topic is about a low power readout ASIC for Time Projection Chambers. Wei. Liu1,2, Zhi. Deng1,2, Fule Li3, Xian Gu3, Yulan Li1,2, Huirong Qi4 1 Department of Engineering Physics, Tsinghua University, Beijing, China 2Key Laboratory of Particle & Radiation Imaging, Ministry of Education, Beijing, China 3Institute of Microelectronics, Tsinghua University, Beijing, China 4Institute of High Energy Physics, Chinese Academy of Science, Beijing, China 2018/11/12 The Workshop on the Circular Electron-Positron Collider

The Workshop on the Circular Electron-Positron Collider CONTENTS Introduction Architecture and Specifications Chip design Test results Summary 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Introduction Architecture and Specifications Chip design Test results summary TPC can provide large-volume high-precision 3D track measurement with stringent material budget In order to achieve high spatial resolution, small pads (e.g. 1mm x 6mm) are needed, resulting ~1 million channel of readout electronics Need low power consumption readout electronics More advanced 65nm process New circuit structure such as SAR-ADC,CR-RC shaper There are about 1 million channels of readout electronics in CEPC-TPC. And , electronics will produce immense heat. So, Low power readout electronics is needed. But ,there are no current existing electronics readout system can fulfill the requirements of such high density and low power consumption. This motivates us to develop ASIC with new circuit structure in the more advanced 65 nm CMOS process. 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Architecture The waveform sampling front end : a preamplifier and a shaper as the analog front-end (AFE), a waveform sampling ADC a dedicated digital signal processing (DSP) and zero-suppression unit and an de-randomize event buffer for each channel. The architecture of the TPC readout electronics is shown in this Figure. It consists of the front-end electronics on the detector panel and the data acquisition system off the detector. They communicate using high-speed serial link. The front-end ASIC consists of analog front-end ,ADC and DSP. We have developed three prototype chips , including Analog Front-end ASIC, SAR-ADC ASIC, Analog Front-end and SAR-ADC ASIC. In the future ,we will develop the DSP . Finally, the Front end ASIC will be developed. Three prototype chips have been designed for the first MPW run Analog Front-end (Charge Sensitive Amplifier + CR-RC shaper) ASIC Lower power SAR-ADC ASIC Analog Front-end +SAR-ADC ASIC 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Specifications AFE(Analog Front-End) Signal Polarity Negative Detector Capacitance 5-20pF Shaper CR-RC Shaping Time 160ns ENC (Equivalent Noise Charge) <500e @ 10pF Dynamic Range 120fC Gain 10mV/fC INL (Integrated Non-Linearity) <1% Crosstalk <0.3% Power Consumption (AFE) <2.5mW/ch SAR-ADC Input Range -0.6V ~ 0.6V diff. Resolution 10bit Sampling Rate 40MS/s DNL <0.65LSB INL <0.6LSB SFDR @ 2MHz, 40MSPS 68dBc SINAD 57dB ENOB >9.2bit @ 2MHz Power Consumption (ADC) <2.5mW/ch The key specifications of the analog front-end ASIC and SAR-ADC ASIC are summarized in this Table. Total power consumption of the two ASIC is 5mW/ch . 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Analog Front-End ASIC Shaper AMP Fully Differential AMP 1320um x 838um IN OUTP OUTN The design strategy for the front-end ASIC is to keep the analog part as simple as possible. Hence we can get the higher power efficiency. In the left Figure , we can see the Analog Front-end ASIC consists of a charge sensitive amplifier, a CR-RC shaper and a difference module. And the layout is shown in the right Figure. CSA AMP The Layout of the Front-End ASIC The Block Diagram of the Analog Front-End ASIC 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary SAR-ADC ASIC 90um x 97um The SAR-ADC instead of pipeline ADC is to get higher power efficiency. The diagram of the SAR-ADC is shown in the left Figure. The layout is shown in the right Figure. The Block Diagram of the SAR-ADC ASIC The Layout of the SAR-ADC ASIC 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Analog Front-End and SAR-ADC ASIC 1800um x 440um The layout of analog front-end and SAR-ADC ASIC is shown in this Figure 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Power consumption:1.93mW/ch Introduction Architecture and Specifications Chip design Test results summary Simulation of Analog Front-End ASIC IN 1fC input charge CSA Power consumption:1.93mW/ch CR Transient simulation of the Analog Front-end ASIC is performed, and the output of key nodes is showed in this Figure. The simulation shows that power consumption is only 1.93mW/ch. OUTP OUTN 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of Analog Front-End ASIC Function Waveform Generator(Agilent33120A) OUTN OUTP OUTN OUTP Digital Phosphor Oscilloscope(DDPO4104 B_L) The test setup for this ASIC is shown in the left Figure. The output of ASIC is shown in the right Figure. And the power consumption is measured to be 2.18mW/ch. OUTP-OUTN OUTP-OUTN i.e. Differential Output ASIC test board Test Setup for the Front-End ASIC Output of the ASIC The Power consumption : 2.18mW/ch 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of Analog Front-End ASIC The Power consumption : 2.18mW/ch We adjust chip bias current through off-chip resistance. And we can get pcb current. The pcb current and chip bias current are linear fitted. We can get the pcb current when the chip doesn’t work . The pcb current when the chip bias current Chip currentAnd the power consumption is measured to be 2.18mW/ch. 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of Analog Front-End ASIC Charge is injected to ASIC from 3fC to 120fC, and the differential output signal is shown in left Figure. The injected charge and differential amplitude are linear fitted. We can get the gain and INL. The gain is 10.5mv/fc. From the right figure, we can see the dynamic range is bigger than 120fc. The maximum INL is 0.41%. The Differential Output Signal Gain Linearity and INL 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of Analog Front-End ASIC The ASIC noise is a function of input capacitance. Increasing the input capacitance increases the noise. The chip was loaded with different capacitor values when measuring the noise. And the ENC is 450e when the input capacitance is 10pF. The noise requirement is 500e. 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of Analog Front-End ASIC Specifications Test Gain 10mV/fC 10.5mV/fC Dynamic Range 120fC >120fC INL( Integral-nonlinearity) <1% 0.41% Power consumption 2.50mW/ch 2.18mW/ch ENC(Equivalent Noise Charge) 500e @ 10pF 450e @ 10pF The test results and specifications are summarized in this table. The power consumption is 2.18mW/ch, It is smaller than specification. So ,power consumption requirement is met. The ENC is measured to be 450e when input capacitance is 10 PF. The ENC requirement is also met. 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of SAR-ADC ASIC The test setup for SAR-ADC ASIC is shown in this Figure. The core power consumption of SAR-ADC ASIC is 1.0mW/ch. And the power requirement has been met. 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Reference buffer module Introduction Architecture and Specifications Chip design Test results summary Test of SAR-ADC ASIC Module name Power（mW） The whole chip 4.0 Reference buffer module 0.25 SAR ADC Core Module 1.0 Other modules 2.75 The test setup for SAR-ADC ASIC is shown in this Figure. The core power consumption of SAR-ADC ASIC is 1.0mW/ch. And the power requirement has been met. 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Test of SAR-ADC ASIC The INL was measured to be 0.5 LSB, and the DNL was measured to be less 0.5LSB. And the SINAD was measured to be 57dB,when the frequency of input signal is 2.4MHz,was sampled at 50MS/s. So, the main requirements of SAR-ADC is met. INL DNL INL DNL SINAD（dB） Specifications <0.6LSB 57dB @2MHz,40MSPS Test <0.5LSB 57dB @2.4MHz,50MSPS 2018/11/12 The Workshop on the Circular Electron-Positron Collider

Architecture and Specifications Chip design Test results summary Introduction Architecture and Specifications Chip design Test results summary Summary Prototype chips of TPC readout have been developed , including the analog front-end ASIC, SAR-ADC ASIC , analog front-end &SAR-ADC ASIC. The test results of the analog front-end ASIC show very promising performance, especially the power consumption. The test results of the SAR-ADC ASIC also show promising performance. Future work -- test the crosstalk of the analog front-end ASIC --test the analog front-end ASIC with TPC --test the analog front-end & SAR-ADC ASIC 2018/11/12 The Workshop on the Circular Electron-Positron Collider

The Workshop on the Circular Electron-Positron Collider THANK YOU 2018/11/12 The Workshop on the Circular Electron-Positron Collider