Download presentation

Presentation is loading. Please wait.

1
**NSoC 3DG Paper & Progress Report**

A 1.8-V 100-MS/s 12-bit Pipelined ADC Date：2009/03/05 Professor：Ko-Chi Kuo Student：Ting-Chang Ma

2
**Paper Information A 1.8-V 100-MS/s 12-bit Pipelined ADC**

This time I will not present a purely paper, I will present our lab’s research about use of papers’ knowledge to implement a high speed and low power analog to digital converter. Our Pipelined ADC is not fully complete. We expected to finish the work by June. The circuits are designing with TSMC P6M CMOS process and 1.8V of supply voltage. Moreover, the UMC 90-nm 1P9M CMOS technology pipelined ADC is designing simultaneously. We expected to finish the work by July. 2009/03/05 AMS

3
**Outline Abstract Introduction Pipelined ADC Architecture**

Implementation of ADC Whole circuit Switch Amplifiers SHA MDAC Conclusion References 2009/03/05 AMS

4
Abstract The digital product increases widely and vastly. Because we live in the analog world, we require a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed and low power analog to digital converter. In this thesis, the circuits are designing with TSMC P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit. 2009/03/05 AMS

5
Introduction 2009/03/05 AMS

6
Introduction Traditionally ADC has many kinds of architecture, including flash, two-stage, successive approximation, and pipeline etc. The advantages and disadvantages will be described in the left figure. Application ∑-∆ ADC: voiceband audio SAR ADC: data acquisition Pipelined: instrumentation video Flash: single event acquisition, video 2009/03/05 AMS

7
**Pipelined ADC Architecture**

2009/03/05 AMS

8
**Pipelined ADC Architecture**

The advantages of the pipeline architecture can conclude in three parts: high speed, lower power, and reusing components. The pipeline ADC consists of many stages. Each stage performs the same job: sampling, holding, quantization in sub-ADC, subtractor, and residue amplifier. The holding signal is quantized by sub-ADC and quantized signal is subtracted by the original signal and the residue is amplified with 2B. Finally the residue signal can be sampled by the following stages. This analog arithmetic unit is usually called as multiplying digital-to-analog converter (MDAC). The MDAC always companies with switched-capacitor circuits. The settling time of MDAC is the primary issue to achieve the maximum speed of the pipelined ADC. 2009/03/05 AMS

9
**Pipelined ADC Architecture (Cont.)**

The advantages of pipeline ADCs are the concurrency of operation by each stage, high throughput, and suitable for high speed application. The speed of pipelined ADC is mainly limited by actions of MDAC. The resolution of pipelined ADC is limited by the performance of sample/hold, MDAC owning to the opamp offset, gain error and mismatch. However the latency is also longer than those of flash or two stage flash converters. The growth of the hardware is linear with the number of bits, e.g. in 1bit/stage of pipeline ADC, N bits ADC require N stage. The application is mainly 8~12bits and 20~200Ms/s. 2009/03/05 AMS

10
**Implementation of ADC Whole circuit**

2009/03/05 AMS

11
**Implementation of ADC Whole circuit**

VinP and VinN are input signals and connected to SHA. The SHA is used to reduce the nonlinearity and improve performance of the ADC. The SHA should have larger bandwidth to achieve better stability. The holding signal from SHA is passed to stage 1 of MDAC. The outputs from MDAC have two types: one is digital signal and the other is residue signal which is passed to next stage. The final stage is a two-bit flash ADC. After the output of two-bit flash ADC is translated, digital correction circuit starts to work. The final output codes are O1~O12. The clock of every stage comes from clock generator. All circuits are simulated with TSMC 0.18um CMOS 1P6M process. 2009/03/05 AMS

12
**Implementation of ADC Switch**

2009/03/05 AMS

13
**Implementation of ADC Switch**

In this thesis, switches used in this work have two types. One is transmission gate and the other is bootstrapped switch. In figure 25, the implementation of bootstrapped switch is shown. The purpose of bootstrapped switch is to make the constant charge injection and then provides the higher linearity. The left part is a booster circuit to ensure that M1 can work properly. The size of capacitor is chosen by the amount of charging on the parasitic capacitor of switches. The purpose of the transistor M2 and M4 is to protect the voltage change of terminals of M3 and M5 exceeding VDD and avoid the breakdown of CMOS individually. 2009/03/05 AMS

14
**Implementation of ADC Switch simulation result**

2009/03/05 AMS

15
**Implementation of ADC Amplifiers**

2009/03/05 AMS

16
**Implementation of ADC Amplifiers**

In this thesis, there are many amplifiers to work in different specifications. Because the requirements of stages along the pipeline chain are relaxed, the sampling capacitor can scale down. In table 6, the specifications of operational amplifier are listed. Due to reduce power consumption, the amplifiers are designed individually. The amplifier of sample and hold circuit is unity gain amplifier, so the bandwidth is lower than 1 MDAC. To keep the high dynamic range with 1.8V, the thermal noise in this circuit also need to reduce. Therefore, the load capacitance is increased to lower noise at expense of the power consumption of operational amplifier for driving large capacitance. 2009/03/05 AMS

17
**Implementation of ADC Amplifiers**

2009/03/05 AMS

18
**Implementation of ADC Amplifiers**

The operational amplifier used in this work is a class A/B folded cascode amplifier. It relaxes the output swing limit of telescopic-cascode-AB op-amp when operating in low voltage. The gain-enhancement amplifier, the architectures of those amplifiers are fully differential. The characteristics of those amplifiers are single transistor, MPIC2 and MNIC2, play a role for circuit of common mode feedback. The gain boosting amplifiers are used to improve the gain with negative feedback action which makes the source voltage of M3, M4, M5 and M6 less sensitive to the output. Therefore, the output impedance is increased. 2009/03/05 AMS

19
**Implementation of ADC Amplifiers**

Using switched-capacitor common mode feedback circuit, as shown in the figure, ensures the common level stable and low power. The reason for this work adopts the SC CMFB circuit is the input swing of CMFB is not limited due to high swing of opamp. Another advantage is no DC power consumed in SC CMFB. 2009/03/05 AMS

20
**Implementation of ADC Amplifiers simulation result**

The frequency response of this amplifier is shown in the figure. The gain is about 91.3dB and the unit-gain frequency is about 535MHz which is large enough to support the application of SHA according to Table 6. 2009/03/05 AMS

21
**Implementation of ADC Amplifiers simulation result**

2009/03/05 AMS

22
**Implementation of ADC SHA**

2009/03/05 AMS

23
**Implementation of ADC SHA**

In the figure, track and hold circuit for ADC is shown. The architecture is flip-around. The feedback factor is almost equal to 1 and it reduces the bandwidth of amplifier and the power consumption of OPAMP. The circuit behaves as following: in holding-to-tracing phase, the switch which is close to amplifier is opened first and then the switch closer to input signal is opened. This is done for reducing the charge injection of switches. 2009/03/05 AMS

24
**Implementation of ADC SHA simulation result**

2009/03/05 AMS

25
**Some key point about measure**

SNR: Signal-to-Noise Ratio SNDR: Signal-to-Noise & Distortion Ratio SFDR: Spurious Free Dynamic Range THD: Total Harmonic Distortion DNL: Differential Nonlinearity INL: Integral Nonlinearity 2009/03/05 AMS

26
**Implementation of ADC SHA simulation result**

2009/03/05 AMS

27
**Implementation of ADC MDAC**

2009/03/05 AMS

28
**Implementation of ADC MDAC**

The circuit of fully differential MDAC for applying to 1.5bits/stage architecture is presented in left figure. It is sampling phase in Φ1 clock and charging the capacitors C1 and C2. It is amplifying phase in Φ1 clock and the output is determined by the charge transfer of capacitor space C1 and C2 and the voltage of DAC. Due to reduce the charge injection, Φ1’ turns off later to Φ1 in sampling mode by using skill of bottom-plate sampling. The bootstrapped switch can be reused by the same path such as the sampling switches s1 and s2. 2009/03/05 AMS

29
**Implementation of ADC MDAC - comparator and decoder**

The schematic of comparator and decoder of MDAC is shown in upper figure. Output signals from comparators are passed to decoder. The output signals from decoder are passed to multiplexer and latches. 2009/03/05 AMS

30
**Implementation of ADC comparator and decoder simulation**

2009/03/05 AMS

31
**Implementation of ADC MDAC simulation result**

2009/03/05 AMS

32
Specification 2009/03/05 AMS

33
Conclusion The 12-bit and 100Ms/s pipeline ADC is designed by HSPICE and Matlab. This thesis focuses on lower power consumption. Therefore, some architectures of ADC are introduced and some issues which affect performance of ADC are also discussed. In order to operating in low voltage, the sampling capacitance should be increased to anti-thermal-noise, but it needs more power consumption. For higher dynamic range in lower supply voltage, the switched-capacitor circuit is adopted. The gain and bandwidth of opamp should be large enough for accuracy and speed by using folded cascode plus gain-boosting technology. The high linearity of switches is also required with bootstrapped switches. The power consumption could be reduced by class A/B architecture, dynamic comparator, and scaling capacitor with following stages. Adopting digital correction circuit can relax the offset error of comparator. 2009/03/05 AMS

34
References 2009/03/05 AMS

35
**Thank you very much for your attention! 2009.03.05**

The End Thank you very much for your attention!

Similar presentations

© 2021 SlidePlayer.com Inc.

All rights reserved.

To make this website work, we log user data and share it with processors. To use this website, you must agree to our Privacy Policy, including cookie policy.

Ads by Google