VLSI System Design LEC3.1 CMOS FABRICATION REVIEW

Slides:

Advertisements

Similar presentations

Pertemuan 5 Fabrikasi IC CMOS

Advertisements

ENGR-45_Lec-06_Diffusion_Fick-1.ppt 1 Bruce Mayer, PE Engineering-45: Materials of Engineering Bruce Mayer, PE Registered Electrical.

CMOS Fabrication EMT 251.

Lecture 0: Introduction

Simplified Example of a LOCOS Fabrication Process

MetalMUMPs Process Flow

CMOS Process at a Glance

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.

Introduction to CMOS VLSI Design Lecture 0: Introduction

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

The Physical Structure (NMOS)

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

SOIMUMPs Process Flow Keith Miller Foundry Process Engineer.

Device Fabrication Example

Introduction Integrated circuits: many transistors on one chip.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

Microelectronic Device Fabrication

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,

Chapter 4 Overview of Wafer Fabrication

SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.

ECE484: Digital VLSI Design Fall 2010 Lecture: IC Manufacturing

Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.

SEMINAR PRESENTATION ON IC FABRICATION PROCESS

Virtual NanoFab A Silicon NanoFabrication Trainer

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated.

Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.

Fabrication Technology(1)

Introduction to Prototyping Using PolyMUMPs

By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.

NanoFab Trainer Nick Reeder June 28, 2012.

Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.

Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.

IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.

©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.

Dynamic Behavior of MOS Transistor. The Gate Capacitance t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap.

CMOS VLSI Fabrication.

CMOS FABRICATION.

Side ViewTop View Beginning from a silicon wafer.

Patterning - Photolithography

CMOS Fabrication EMT 251.

CMOS VLSI Design Lecture 2: Fabrication & Layout

Lecture 2 State-of-the art of CMOS Technology

1. Introduction. Diseño de Circuitos Digitales para Comunicaciones Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration.

IC Manufactured Done by: Engineer Ahmad Haitham.

CMOS Fabrication CMOS transistors are fabricated on silicon wafer

Fabrication Process terms

Manufacturing Process I

CMOS Process Flow.

Chapter 1 & Chapter 3.

Digital Integrated Circuits A Design Perspective

Silicon Wafer cm (5’’- 8’’) mm

LEC 3.2 LAYOUT D E S I G N R U L E S & DESIGN RULE CHECKER (DRC)

_________ ______ _________ (with extended comments)

Add nitride Silicon Substrate.

Lecture #25 OUTLINE Device isolation methods Electrical contacts to Si

CMOS半導體製程概念 INVERTER.

Manufacturing Process I

Manufacturing Process I

CSE 87 Fall 2007 Chips and Chip Making

Presentation transcript:

VLSI System Design LEC3.1 CMOS FABRICATION REVIEW Engr. Anees ul Husnain ( anees.buzdar@gmail.com ) Department of Computer Systems Engineering, College of Engineering & Technology, IUB

A review up till now… Cross Sectional views of a transistor

Fabricating one transistor Oxidation (Field oxide) Silicon substrate Silicon dioxide oxygen Photoresist Develop oxide Coating photoresist Mask-Wafer Alignment and Exposure Mask UV light Exposed exposed Polysilicon Deposition polysilicon Silane gas Dopant gas Oxidation (Gate oxide) gate oxide oxygen Photoresist Remove oxide RF Power Ionized oxygen gas Oxide Etch photoresist Ionized CF4 gas Mask and Etch Ionized CCl4 gas poly gate G S D Active Regions top nitride silicon nitride Nitride Deposition Contact holes Etch Ion Implantation resist ox Scanning ion beam Metal Deposition and Etch drain Metal contacts

Top view

Wafer preparation

Start with P substrate Start  Target structure

1. Spin Resist Coating Target structure

2. Expose N Well Mask to UV light Target structure

3. Develop resist Target structure

4. Implant N Well Target structure

Anneal wafer to diffuses N well (heal lattice) and grow new oxide layer Target structure

5. Remove Resist Target structure

Remove oxide from anneal Target structure

1. Spin Resist Target structure

2. Expose resist with active diffusion mask Target structure

3. Develop resist Target structure

4. Grow oxide on exposed surface Target structure

5. Strip resist Target structure

Grown thin oxide over silicon surfaces Target structure

1. Deposit poly using Chemical Vapor Deposition (CVD) Target structure

2. Spin resist 3. expose resist using the GATE mask 4. develop resist 5. etch poly Target structure

Remove thin oxide layer where exposed Target structure

1. Spin resist 2. expose with P implant mask 3. develop resist 4 1. Spin resist 2. expose with P implant mask 3. develop resist 4. implant P 5. strip resist Target structure

1. Spin resist 2. expose with N implant mask 3. develop resist 4 1. Spin resist 2. expose with N implant mask 3. develop resist 4. implant N 5. strip resist Target structure

Remove resist – anneal wafer – oxide etch Target structure

Grow oxide 1. spin resist 2. expose Contact mask 3. develop resist 4 Grow oxide 1. spin resist 2. expose Contact mask 3. develop resist 4. etch contacts 5. strip resist Target structure

1. Deposit metal L1 2. spin resist 3. expose metal L1 mask 4 1. Deposit metal L1 2. spin resist 3. expose metal L1 mask 4. develop resist 5. etch metal 6. strip resist Target structure

Rest of metal layers follow similarly Target structure