1. LEC 3.2 LAYOUT D E S I G N R U L E S & DESIGN RULE CHECKER (DRC)
VLSI System Design
LEC 3.2 LAYOUT D E S I G N R U L E S & DESIGN RULE CHECKER (DRC)
Engr. Anees ul Husnain ( )
Department of Computer Systems Engineering,
College of Engineering & Technology, IUB

2. LAYOUT DESIGN RULES
Design Rules: Bridges between technology capability and design considerations

4. Summary of Terminology
body
diffusion (n/p)
source
drain
well
tap
contact
metal track
via
polysilicon gate length/width
gate oxide
channel
All these structures must obey the dimensions and separation rules dictated by the process fabrication facility

7. Process design rules Design rules change from fab to fab
Fab examples: IBM, Intel, TI, TSMC, UMC, MOSIS
Design rules change according to the process technology

8. Lambda rules
Feature Size: minimum distance between source and drain of transistor
Feature size = 2λ 90nm feature size λ=45)
According to Moore’s Law, how much does the feature size scale by every ~2 years?

9. Design rules and gate layout
Lambda rules are conservative

10. More design rules MOSIS MOSIS Categories: MOS Interconnect Systems
A commercial semi conductor manufacturing company.
MOSIS Rules became standards.
MOSIS Categories:
SCMOS
SUBM
DEEP

11. MOSIS design rules

12. MOSIS design rules

13. Layout of a 3-input NAND gate

14. DESIGN RULE CHECKER
To verify the design parameters set by the design engineering so that it doesn’t exceeds from the allowable limit provided by the fabrication engineer