Multi-Cycle CPU.

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Presentation transcript:

Multi-Cycle CPU

Multi-Cycle CPU Combine Functional Units Reuse for different phases of instructions One ALU for PC increment Branch target computation Address computation for memory access R-Type instruction execution One memory unit for both instructions and data Multiple but Shorter Clock Cycles Different instructions take different number of cycles Average CPI times cycle time gives better performance

F A D A B B E C PCWrite Mem Read Mem Write IRWrite RegWrite ALUOp PC To Control 31-26 0 M 1 U 2 X Shift Left 2 25-0 PCWrite F PC 31-28 Zero Mem Read Mem Write PC A D IRWrite RegWrite 0 M U 1 X 0 M U 1 X 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory B Registers 0 M U 1 X 0 M 1 U 2 X 3 Read Data 2 B Mem Data Write Reg 4 Write Data 15-11 Write Data E C 0 M U 1 X Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl 5-0 ALUOp

F A D A B B C E PCWrite Mem Read Mem Write IRWrite RegWrite ALUOp PC To Control 31-26 Shift Left 2 1 2 25-0 PCWrite PC 31-28 F Zero Mem Read Mem Write PC A D IRWrite RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl 5-0 ALUOp

Instruction Fetch/PC Increment To Control 31-26 Shift Left 2 1 2 25-0 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl 5-0 ALUOp ADD Instruction Fetch/PC Increment

Instruction Decode/Register Fetch/Branch Target To Control 31-26 Shift Left 2 1 2 25-0 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory IR B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Decode/Register Fetch/Branch Target

Branch Completion (Branch Taken) PCWriteCond To Control 31-26 Shift Left 2 1 2 25-0 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp SUB Branch Completion (Branch Taken)

Instruction Fetch after Branch Completion To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Fetch after Branch Completion

Instruction Decode/Register Fetch/Branch Target To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Decode/Register Fetch/Branch Target

R-Type Instruction Execution To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp Function R-Type Instruction Execution

R-Type Instruction Write Back To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp R-Type Instruction Write Back

Instruction Fetch After R-Type To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Fetch After R-Type

Instruction Decode/Register Fetch/Branch Target To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Decode/Register Fetch/Branch Target

Address Computation (lw or sw) To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Address Computation (lw or sw)

Memory Access for lw F A D A B B C E PCWrite Mem Read Mem Write To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp Memory Access for lw

Write Back for lw F A D A B B C E PCWrite Mem Read Mem Write IRWrite To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp Write Back for lw

Instruction Fetch after lw To Control 31-26 1 2 25-0 Shift Left 2 PCWrite PC 31-28 F Zero Mem Read Mem Write A D PC IRWrite RegWrite 1 1 25-21 Read/Write Addr Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 Memory IR ALU Out B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg 15-0 Shift Left 2 Sign Ext ALU Ctrl 5-0 ALUOp ADD Instruction Fetch after lw

F A D A B B C E PCWrite Mem Read Mem Write IRWrite RegWrite ALUOp PC To Control 31-26 Shift Left 2 1 2 25-0 PCWrite PC 31-28 F Zero Mem Read Mem Write PC A D IRWrite RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory B Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data C 1 E Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl 5-0 ALUOp

Control A B ALUOp PCWriteCond PCSrc PCWrite MemWrite ALUSrcA MemRead 31-26 1 2 Shift Left 2 PCWrite 25-0 PC 31-28 Zero MemWrite ALUSrcA MemRead PC IorD IRWrite RegDst RegWrite 1 1 25-21 Read/Write Addr IR Read Reg 1 Read Data 1 A 20-16 A L U Read Reg 2 ALU Out Memory Registers 1 Read Data 2 B 1 2 3 Mem Data Write Reg 4 Write Data 15-11 Write Data 1 ALUSrcB Mem Data Reg Sign Ext Shift Left 2 15-0 ALU Ctrl MemtoReg 5-0 ALUOp

Control Lines PCWriteCond Write PC conditionally on branch PCWrite Write PC for increment or jump PCSrc Select source for writing to PC IorD Select address for memory read/write MemRead Read from memory (instruction or data) MemWrite Write to memory (store word) IRWrite Write to Instruction Register

Control Lines MemtoReg Select memory or ALUOut to write to register RegDst Select field to select destination register RegWrite Write to selected register ALUSrcA Select source for upper ALU input ALUSrcB Select source for lower ALU input ALUOp Select ALU operation or set to function code: 00 = Add, O1 = Subtract, 10 = use funct field (bits 0-5)

Clock Cycles 1. Instruction Fetch, PC Increment 2. Instruction Decode, Register Fetch, Branch Target Computation 3. R-type Execution or Memory Address Computation or Branch Completion 4. R-type Write Back or Memory Access 5. Memory write back

Control Overview Instruction Fetch Instruction Decode Start Memory Access R-type Branch Jump

Control: Finite State Machine Instruction Fetch 0 Instruction Decode 1 MemRead IorD = 0 IRWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 PCWrite ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Start lw or sw R-type beq j Memory Access FSM Branch FSM Jump FSM R-type FSM

Memory Access FSM Memory Address Comp 2 From State 1 lw or sw Memory ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Memory Access lw 3 lw sw MemRead IorD = 1 MemWrite IorD = 1 Memory Access sw 5 Write Back 4 RegWrite MemToReg = 1 RegDst = 0 To State 0

R-type FSM From State 1 R-type Execution 6 Write Back 7 To State 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 Execution 6 RegDst = 1 RegWrite MemtoReg = 0 Write Back 7 To State 0

Branch FSM From State 1 beq Branch Completion 8 To State 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSrc = 01 Branch Completion 8 To State 0

Jump FSM From State 1 j Jump Completion 9 To State 0 PCWrite PCSrc = 10 Jump Completion 9 To State 0

Complete Finite State Machine Instruction Fetch 0 MemRead IorD = 0 IRWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 00 PCSrc = 00 PCWrite Instruction Decode 1 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Start lw or sw R-type j beq ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 Memory Address Comp 2 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 Execution 6 Jump Completion 9 PCWrite PCSrc = 10 lw sw Memory Access lw 3 MemRead IorD = 1 Branch Completion 8 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSrc = 01 MemWrite IorD = 1 RegDst = 1 RegWrite MemtoReg = 0 Memory Access sw 5 Write Back 7 RegWrite MemToReg = 1 RegDst = 0 Write Back 4

FSM Implementation as PLA Opcode from IR PLA Clock State Register PCWrite ALUOp PCWriteCond ALUSrcB PCSrc IorD ALUSrcA MemRead RegWrite MemWrite RegDst IRWrite MemtoReg