1. .1 1999 ©UCB CS 161Computer Architecture Chapter 5 Lecture 11 Instructor: L.N. Bhuyan www.cs.ucr.edu/~bhuyan Adapted from notes by Dave Patterson (http.cs.berkeley.edu/~patterson)

2. .2 1999 ©UCB Implementing Main Control Main Control RegDst Branch MemRead MemtoReg ALUop MemWrite ALUSrc RegWrite op 2 Main Control has one 6-bit input, 9 outputs (7 are 1-bit, ALUOp is 2 bits) To build Main Control as sum-of-products: (1) Construct a minterm for each different instruction (or R-type); each minterm corresponds to a single instruction (or all of the R- type instructions), e.g., M R-format, M lw (2) Determine each main control output by forming the logical OR of relevant minterms (instructions), e.g., RegWrite: M R-format OR M lw

3. .3 1999 ©UCB Single-Cycle MIPS-lite CPU Regs Read Reg1 Read data1 ALUALU Read data2 Read Reg2 Write Reg Write Data Zero ALU- con RegWrite Address Read data Write Data Sign Extend Dmem MemRead MemWrite MuxMux MemTo- Reg MuxMux Read Addr Instruc- tion Imem 4 PCPC addadd addadd << 2 MuxMux ALU Control 5:0 ALUOp (2) ALU- src MuxMux 25:21 20:16 15:11 RegDst 15:0 31:0 Branch Main Control op=[31:26] PCSrc

4. .4 1999 ©UCB Fig. 5.17 Datapath with Control Signals

5. .5 1999 ©UCB Fig. 5.18 Setting Control Lines Depend on Opcode

6. .6 1999 ©UCB Control Design °Simple combinational logic (truth tables)

7. .7 1999 ©UCB Fig. 5.19 R-type operation, add $t1, $t2, $t3 Active parts are highlighted

8. .8 1999 ©UCB Fig. 5.20 Active parts for a Load instruction

9. .9 1999 ©UCB Fig. 5.21 Active parts for a beq instruction

10. .10 1999 ©UCB Fig. 5.24 Extension for Jump instruction

11. .11 1999 ©UCB Single-Cycle Machine: Appraisal °All instructions complete in one clock cycle (CPI = 1) °Some instructions take more steps than others lw is most expensive (5 steps, vs. 4 for R-type and sw, 3 for beq ) °Clock cycle must cover longest instruction  inefficient suppose mul is added? 32-shift/add steps  would delay every other instruction

12. .12 1999 ©UCB Example °Assume 2ns for instruction/data memory, 1ns for decode/register read, 2ns for ALU and 1 ns for register write. °Single-cycle datapath clock period = 8 ns. °Assume an instn mix of 24% loads, 12% stores, 44% R-format, 18% branches, and 2% jumps. °Assuming a variable-cycle datapath, average clock period = 6.3 ns. °Possible Speed-up = 1.27

13. .13 1999 ©UCB Multicycle Implementation (MIPS-lite v.2) °Want more efficient implementation °Each step will take one clock cycle (not each instruction) [CPI > 1]  shorter clock cycle: cycle time constrained by longest step, not longest instruction °simpler instructions take fewer cycles  higher overall performance °complex control: finite state machine °Versatile (can extend for new instructions: add3, swap, etc.)

14. .14 1999 ©UCB Recap: Clocking: single-cycle vs. multicycle add $t0,$t1,$t2 beq $t0,$t1,L Single-cycle Implementation Multicycle Implementation add $t0,$t1,$t2 beq $t0,$t1,L Multicycle Implementation: less waste=higher performance waste clock

15. .15 1999 ©UCB Recap: How fast can we run the clock? °Depends on how much want done per clock cycle Can do: several “inexpensive” datapath operations per clock -simple gates (AND, OR, …) -single datapath registers (PC) -sign extender, left shifter, multiplexor PLUS: exactly one “expensive” datapath operation per clock -ALU operation -Register File access (2 reads, or 1 write) -Memory access (read or write)

16. .16 1999 ©UCB Multicycle Datapath (overview) Registers Read Reg1 ALUALU Read Reg2 Write Reg Data PCPC Address Instruction or Data Memory MIPS-lite Multicycle Version A B ALU- Out Instruction Register Data Memory Data Register Read data 1 Read data 2 One ALU (no extra adders) One Memory (no separate Imem, Dmem) New Temporary Registers (“clocked”/require clock input)

17. .17 1999 ©UCB Multicycle Implementation °Datapath changes one memory: both instructions and data (because can access on separate steps) one ALU (eliminate extra adders) extra “invisible” registers to capture intermediate (per-step) datapath results °Controller changes controller must fire control lines in correct sequence and correct time  controller must remember current execution step, advance to next step

18. .18 1999 ©UCB Multicycle Datapath: Add Multiplexors ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 zero 15:11 Note inputs to multiplexors

19. .19 1999 ©UCB Datapath + Control Points ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA ALUSrcB MemtoReg ALU Control ALUOp 2 2 3 (funct) 5:0 MuxMux PCSrc PCWrite PCWrite- Cond

20. .20 1999 ©UCB Multicycle Instruction Execution °All instructions execute in 3-5 cycles 3 cycles: beq 4 cycles:R-type, sw 5 cycles: lw °1: fetch instruction, PC=PC+4 °2: decode, fetch registers, brnch target °3: execute/compute address/branch °4: access memory/complete R-type °5: ( lw ) store memory

21. .21 1999 ©UCB Cycle 1 Datapath: IR=Mem[PC]; PC=PC+4 ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 2 3 (funct) 5:0 MuxMux IR=Mem[PC]; PC=PC+4

22. .22 1999 ©UCB Cycle 2: A=Reg[IR25:21]; ALUOut= PC + sgn-ext(IR15:0) << 2 ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 2 3 (funct) 5:0 MuxMux A=Reg[IR 25:21 ]; B=Reg[IR 20:16 ]; ALUOut= PC + sgn-ext(IR 15:0 ) << 2

23. .23 1999 ©UCB Cycle 3: R-format: ALUOut = A op B ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 2 3 (funct) 5:0 MuxMux ALUOut=A op B

24. .24 1999 ©UCB Cycle 4 R-format: Reg[IR15:11] = ALUOut ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 2 3 (funct) 5:0 MuxMux Reg[IR 15:11 ] = ALUOut How many times use ALU?

25. .25 1999 ©UCB Cycle 3 beq: if (A==B) PC =ALUOut ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 2 3 (funct) 5:0 MuxMux if (A==B) PC =ALUOut

26. .26 1999 ©UCB Cycle 3 lw: ALUOut = A + sgn-ext(IR15:0) ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=x MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=1 ALUSrcB=2 MemtoReg=x ALU Control ALUOp=0 2 2 3 (funct) 5:0 MuxMux PCSrc=x PCWrite PCWrite- Cond ALUOut = A + sgn-ext(IR 15:0 )

27. .27 1999 ©UCB Cycle 4 lw : MDR = Mem[ALUout] ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=1 MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=x ALUSrcB=x MemtoReg=x ALU Control ALUOp=x 2 2 3 (funct) 5:0 MuxMux PCSrc=x PCWrite PCWrite- Cond MDR = Mem[ALUout]

28. .28 1999 ©UCB Cycle 5 lw: Reg[IR15:11] = MDR ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=x MemRead MemWrite IRWrite RegDst=0 RegWrite ALUSrcA=x ALUSrcB=x MemtoReg=1 ALU Control ALUOp=x 2 2 3 (funct) 5:0 MuxMux PCSrc=x PCWrite PCWrite- Cond Reg[IR 15:11 ] = MDR

29. .29 1999 ©UCB Cycle 4 ( sw ): Mem[ALUOut] = B ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=1 MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA ALUSrc MemtoReg ALU Control ALUOp 2 2 3 (funct) 5:0 MuxMux PCSrc PCWrite PCWrite- Cond Mem[ALUOut] = B