1. ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2014 Datapath and Control (Chapter 4)
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
Fall 2014, Sep
ELEC / Lecture 5

2. Von Neumann Kitchen ALU Start Control My choice PC Registers Processor
Program
Data
Input
Memory
Output
Fall 2014, Sep
ELEC / Lecture 5

3. Where Does It All Begin? In a register called program counter (PC).
PC contains the memory address of the next instruction to be executed.
In the beginning, PC contains the address of the memory location where the program begins.
Fall 2014, Sep
ELEC / Lecture 5

4. Where is the Program? Processor Memory Program counter (register)
Machine code
of program
Start
address
Fall 2014, Sep
ELEC / Lecture 5

5. How Does It Run? Start PC has memory address where program begins
Fetch instruction word from memory address in PC
and increment PC ← PC + 4 to point to next instruction
Decode instruction
Execute instruction
Save result in register or memory No
Program
complete?
Yes
STOP
Fall 2014, Sep
ELEC / Lecture 5

6. Datapath and Control
Datapath: Memory, registers, adders, ALU, and communication buses. Each step (fetch, decode, execute, save result) requires communication (data transfer) paths between memory, registers and ALU.
Control: Datapath for each step is set up by control signals that set up dataflow directions on communication buses and select ALU and memory functions. Control signals are generated by a control unit consisting of one or more finite-state machines.
Fall 2014, Sep
ELEC / Lecture 5

7. Datapath for Instruction Fetch
Add 4
Instruction
Memory PC
Instruction
word to
control unit
and registers
Address
Fall 2014, Sep
ELEC / Lecture 5

8. Register File: A Datapath Component5
32 Registers
(reg. file)
reg 1 32
Read
registers
reg 1 data 5
reg 2
Write
register 5 32
reg 2 data
Write data 32
RegWrite
from control
Fall 2014, Sep
ELEC / Lecture 5

9. Multi-Operation ALU Operation select from control 3 zero ALU result
Operation select ALU function
000 AND
001 OR
010 Add
110 Subtract
111 Set on less than 3
zero
ALU
result
overflow
zero = 1, when all bits of result are 0
Fall 2014, Sep
ELEC / Lecture 5

10. R-Type Instructions Also known as arithmetic-logical instructions
add, sub, slt
Example: add $t0, $s1, $s2
Machine instruction word
opcode $s1 $s2 $t0 function
Read two registers
Write one register
Opcode and function code go to control unit that generates RegWrite and ALU operation code.
Fall 2014, Sep
ELEC / Lecture 5

11. Datapath for R-Type Instruction
opcode $s1 $s2 $t function (add)
Operation
select
from control (add) 5
32 Registers
(reg. file)
10001
$s1
Read
register
numbers 3 32
zero 5
10010
$s2
ALU
result 32
overflow
Write reg.
number 5
01000
$t0
Write data 32
RegWrite
from control
activated
Fall 2014, Sep
ELEC / Lecture 5

12. Load and Store Instructions
I-type instructions
lw $t0, 1200 ($t1) # incr. in bytes
opcode $t1 $t
sw $t0, 1200 ($t1) # incr. in bytes
Fall 2014, Sep
ELEC / Lecture 5

13. Datapath for lw Instruction
opcode $t $t
MemWrite
Operation
select
from control
(add)
32 Registers
(reg. file) 5
01001
$t1
Read
register
numbers 3 32
Read
data 5
zero
result
ALU
Addr.
Data
memory
overflow
Write reg.
number 5
01000
$t0
Write
data
Write data 32 32
RegWrite
from control
activated
Sign
extend
MemRead
activated 16
mem. data to $t0
Fall 2014, Sep
ELEC / Lecture 5

14. Datapath for sw Instruction
opcode $t $t
MemWrite
activated
Operation
select
from control
(add)
32 Registers
(reg. file) 5
01001
$t1
Read
register
numbers 3 32
Read
data 5
zero
01000
$t0
result
ALU
Addr.
Data
memory
overflow
Write reg.
number 5 32
Write
data
Write data
$t0 data to mem. 32 32
Sign
extend
RegWrite
from control
MemRead 16
Fall 2014, Sep
ELEC / Lecture 5

15. Branch Instruction (I-Type)
beq $s1, $s2, 25 # if $s1 = $s2, advance PC through instructions
16-bits
opcode $s1 $s
Note: Can branch within ± 215 words from the current instruction
address in PC.
Fall 2014, Sep
ELEC / Lecture 5

16. Datapath for beq Instruction
16-bits
opcode $s $s2 25
Operation
select
from control (subtract)
32 Registers
(reg. file) 5
10001
$s1
Read
register
numbers 32
ALU 3 5
10010
$s2
To branch
control
logic
zero
result 5 32
Write reg.
number
overflow
Write data
Add
PC+4
Branch
target 32
RegWrite
from control
From instruction
fetch datapath 32
Sign
extend
Shift
left 2 16 32 32 32
Fall 2014, Sep
ELEC / Lecture 5

17. J-Type Instruction j 2500 # jump to instruction 2,500 26-bits
opcode ,500
32-bit jump address
bits from PC+4
Fall 2014, Sep
ELEC / Lecture 5

18. Datapath for Jump Instruction
Branch
Jump
Add
Branch
addr. 4 1
mux 32 32
mux 1 32
PC+4 4
Shift
left 2 28
Instruction
Memory 32 PC 26
opcode (bits 26-31)
to control 32 6
Address 32
Instruction
word to
control and
registers
Fall 2014, Sep
ELEC / Lecture 5

19. ALU ALU Data mem. Combined Datapaths 0 mux 1 Add 1 mux 0 opcode
Jump
0-25
Shift
left 2
0 mux 1 4
Add
1 mux 0
ALU
Branch
opcode
MemtoReg
CONTROL
RegDst
26-31
21-25
zero
MemWrite
MemRead
ALU
Instr.
mem. PC
Reg. File
Data
mem.
16-20
1 mux 0
0 mux 1
1 mux 0
Combined
Datapaths
11-15
ALU
Cont.
Sign
ext.
Shift
left 2
0-15
0-5
Fall 2014, Sep
ELEC / Lecture 5

20. Control RegDst Jump Branch MemRead MemtoReg ALUOp MemWrite ALUSrc
RegWrite
Instruction
bits 26-31
opcode
Control
Logic 2
Instruction
bits 0-5
funct.
ALU Control
to ALU
Fall 2014, Sep
ELEC / Lecture 5

21. Control Logic: Truth Table
Instr type
Inputs: instr. opcode bits
Outputs: control signals 31 30 29 28 27 26
RegDst
Jump
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALOOp1
ALUOp2 R 1 lw sw X
beq j
Fall 2014, Sep
ELEC / Lecture 5

22. How Long Does It Take?
Assume control logic is fast and does not affect the critical timing. Major time delay components are ALU, memory read/write, and register read/write.
Arithmetic-type (R-type)
Fetch (memory read) 2ns
Register read 1ns
ALU operation 2ns
Register write 1ns
Total 6ns
Fall 2014, Sep
ELEC / Lecture 5

23. Time for lw and sw (I-Types)
ALU (R-type) 6ns
Load word (I-type)
Fetch (memory read) 2ns
Register read 1ns
ALU operation 2ns
Get data (mem. Read) 2ns
Register write 1ns
Total ns
Store word (no register write) 7ns
Fall 2014, Sep
ELEC / Lecture 5

24. Time for beq (I-Type) ALU (R-type) 6ns Load word (I-type) 8ns
Store word (I-type) 7ns
Branch on equal (I-type)
Fetch (memory read) 2ns
Register read 1ns
ALU operation 2ns
Total ns
Fall 2014, Sep
ELEC / Lecture 5

25. Time for Jump (J-Type) ALU (R-type) 6ns Load word (I-type) 8ns
Store word (I-type) 7ns
Branch on equal (I-type) 5ns
Jump (J-type)
Fetch (memory read) 2ns
Total ns
Fall 2014, Sep
ELEC / Lecture 5

26. How Fast Can Clock Run?
If every instruction is executed in one clock cycle, then:
Clock period must be at least 8ns to perform the longest instruction, i.e., lw.
This is a single cycle machine.
It is slower because many instructions take less than 8ns but are still allowed that much time.
Method of speeding up: Use multicycle datapath.
Fall 2014, Sep
ELEC / Lecture 5

27. A Single Cycle Example Delay of 1-bit full adder = 1ns
Clock period ≥ 32ns
a31 . a2 a1 a0
c32
1-b full
adder
s31 . s2 s1 s0
1-b full
adder
b31 . b2 b1 b0
1-b full
adder
1-b full
adder
Time of adding words ~ 32ns
Time of adding bytes ~ 32ns
Fall 2014, Sep
ELEC / Lecture 5

28. A Multicycle Implementation. a2 a1 a0
Delay of 1-bit full adder = 1ns
Clock period ≥ 1ns
Time of adding words ~ 32ns
Time of adding bytes ~ 8ns
Shift
1-b full
adder
b31 . b2 b1 b0
s31 . s2 s1 s0
c32 FF
Shift
Shift
Initialize
to 0
Fall 2014, Sep
ELEC / Lecture 5

29. ALU ALU Data mem. Single-cycle Datapaths 0 mux 1 Add 1 mux 0 opcode
Jump
0-25
Shift
left 2
0 mux 1 4
Add
1 mux 0
ALU
Branch
opcode
MemtoReg
CONTROL
RegDst
26-31
21-25
zero
MemWrite
MemRead
ALU
Instr.
mem. PC
Reg. File
Data
mem.
16-20
1 mux 0
0 mux 1
1 mux 0
Single-cycle
Datapaths
11-15
ALU
Cont.
Sign
ext.
Shift
left 2
0-15
0-5
Fall 2014, Sep
ELEC / Lecture 5

30. Multicycle Datapath Memory ALU Instr. reg. (IR) A Reg. PC
Addr.
Memory
Register file
ALU
ALUOut Reg.
Data 4
Mem. Data (MDR)
B Reg.
One-cycle data transfer paths
(need registers to hold data)
Fall 2014, Sep
ELEC / Lecture 5

31. Multicycle Datapath Requirements
Only one ALU, since it can be reused.
Single memory for instructions and data.
Five registers added:
Instruction register (IR)
Memory data register (MDR)
Three ALU registers, A and B for inputs and ALUOut for output
Fall 2014, Sep
ELEC / Lecture 5

32. Multicycle Datapath Memory ALU Instr. reg. (IR) A Reg. PC
PCSource
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
11-15
Register file
ALU
ALUSrcA
ALUSrcB
ALUOut Reg.
IorD
Data
Mem. Data (MDR)
B Reg.
out
RegDst
MUX
control
IRWrite 4
in1
in2
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALU
control
ALUOp
0-5
Fall 2014, Sep
ELEC / Lecture 5

33. 3 to 5 Cycles for an Instruction
Step
R-type
(4 cycles)
Mem. Ref.
(4 or 5 cycles)
Branch type
(3 cycles)
J-type
Instruction fetch
IR ← Memory[PC]; PC ← PC+4
Instr. decode/ Reg. fetch
A ← Reg(IR[21-25]); B ← Reg(IR[16-20])
ALUOut ← PC + {(sign extend IR[0-15]) << 2}
Execution, addr. Comp., branch & jump completion
ALUOut ←
A op B
A+sign extend
(IR[0-15])
If (A= =B)
then
PC←ALUOut
PC←PC[28-31] ||
(IR[0-25]<<2)
Mem. Access or R-type completion
Reg(IR[11-15]) ← ALUOut
MDR←M[ALUout] or M[ALUOut]←B
Memory read completion
Reg(IR[16-20]) ← MDR
Fall 2014, Sep
ELEC / Lecture 5

34. Cycle 1 of 5: Instruction Fetch (IF)
Read instruction into IR, M[PC] → IR
Control signals used:
IorD = 0 select PC
MemRead = 1 read memory
IRWrite = 1 write IR
Increment PC, PC + 4 → PC
ALUSrcA = 0 select PC into ALU
ALUSrcB = 01 select constant 4
ALUOp = 00 ALU adds
PCSource = 00 select ALU output
PCWrite = 1 write PC
Fall 2014, Sep
ELEC / Lecture 5

35. Cycle 2 of 5: Instruction Decode (ID) R I J
opcode | reg 1 | reg 2 | reg 3 | shamt | fncode
opcode | reg 1 | reg 2 | word address increment
opcode | word address jump
Control unit decodes instruction
Datapath prepares for execution
R and I types, reg 1→ A reg, reg 2 → B reg
No control signals needed
Branch type, compute branch address in ALUOut
ALUSrcA = 0 select PC into ALU
ALUSrcB = 11 Instr. Bits 0-15 shift 2 into ALU
ALUOp = 00 ALU adds
Fall 2014, Sep
ELEC / Lecture 5

36. Cycle 3 of 5: Execute (EX)
R type: execute function on reg A and reg B, result in ALUOut
Control signals used:
ALUSrcA = 1 A reg into ALU
ALUsrcB = 00 B reg into ALU
ALUOp = 10 instr. Bits 0-5 control ALU
I type, lw or sw: compute memory address in ALUOut ← A reg + sign extend IR[0-15]
ALUSrcB = 10 Instr. Bits 0-15 into ALU
ALUOp = 00 ALU adds
Fall 2014, Sep
ELEC / Lecture 5

37. Cycle 3 of 5: Execute (EX)
I type, beq: subtract reg A and reg B, write ALUOut to PC
Control signals used:
ALUSrcA = 1 A reg into ALU
ALUsrcB = 00 B reg into ALU
ALUOp = 01 ALU subtracts
If zero = 1, PCSource = 01 ALUOut to PC
If zero = 1, PCwriteCond =1 write PC
Instruction complete, go to IF
J type: write jump address to PC ← IR[0-25] shift 2 and four leading bits of PC
PCSource = 10
PCWrite = 1 write PC
Fall 2014, Sep
ELEC / Lecture 5

38. Cycle 4 of 5: Reg Write/Memory
R type, write destination register from ALUOut
Control signals used:
RegDst = 1 Instr. Bits specify reg.
MemtoReg = 0 ALUOut into reg.
RegWrite = 1 write register
Instruction complete, go to IF
I type, lw: read M[ALUOut] into MDR
IorD = 1 select ALUOut as mem adr.
MemRead = 1 read memory to MDR
I type, sw: write M[ALUOut] from B reg
MemWrite = 1 write memory
Fall 2014, Sep
ELEC / Lecture 5

39. Cycle 5 of 5: Reg Write I type, lw: write MDR to reg[IR(16-20)]
Control signals used:
RegDst = 0 instr. Bits are write reg
MemtoReg = 1 MDR to reg file write input
RegWrite = 1 write reg. file
Instruction complete, go to IF
For an alternative method of designing datapath, see
N. Tredennick, Microprocessor Logic Design, the Flowchart Method,
Digital Press, 1987.
Fall 2014, Sep
ELEC / Lecture 5

40. 1-bit Control Signals Signal name Value = 0 Value =1 RegDst
Write reg. # = bit 16-20
Write reg. # = bit 11-15
RegWrite
No action
Write reg. ← Write data
ALUSrcA
First ALU Operand ← PC
First ALU Operand←Reg. A
MemRead
Mem.Data Output←M[Addr.]
MemWrite
M[Addr.]←Mem. Data Input
MemtoReg
Reg.File Write In←ALUOut
Reg.File Write In←MDR
IorD
Mem. Addr. ← PC
Mem. Addr. ← ALUOut
IRWrite
IR ← Mem.Data Output
PCWrite
PC is written
PCWriteCond
PC is written if zero(ALU)=1
zero(ALU)
PCWriteCond
PCWrite etc.
PCWrite
Fall 2014, Sep
ELEC / Lecture 5

41. 2-bit Control Signals Signal name Value Action ALUOp 00
ALU performs add 01
ALU performs subtract 10
Funct. field (0-5 bits of IR ) determines ALU operation
ALUSrcB
Second input of ALU ← B reg.
Second input of ALU ← 4 (constant)
Second input of ALU ← 0-15 bits of IR sign ext. to 32b 11
Second input of ALU ← 0-15 bits of IR sign ext. and left shift 2 bits
PCSource
ALU output (PC +4) sent to PC
ALUOut (branch target addr.) sent to PC
Jump address IR[0-25] shifted left 2 bits, concatenated with PC+4[28-31], sent to PC
Fall 2014, Sep
ELEC / Lecture 5

42. Control: Finite State Machine
Start
State 0
Clock
cycle 1
Instruction fetch
State 1
Clock
cycle 2
Instruction decode and register fetch
FSM-M
Memory
access
instr.
FSM-R
FSM-B
FSM-J
Clock
cycles 3-5
R-type
instr.
Branch
instr.
Jump
instr.
Fall 2014, Sep
ELEC / Lecture 5

43. State 0: Instruction Fetch (CC1)
PCSource=00
PCWrite
etc.=1
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALU
ALUSrcA=0
ALUSrcB=01
ALUOut Reg.
IorD=0
Data
Mem. Data (MDR)
B Reg.
out
RegDst
MUX
control
IRWrite =1 4
Add
in1
in2
MemRead = 1
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALUOp
=00
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

44. State 0 Control FSM Outputs
Start
State 1
Instruction decode/
Register fetch/
Branch addr.
State0
Instruction
fetch
MemRead =1
ALUSrcA = 0
IorD = 0
IRWrite = 1
ALUSrcB = 01
ALUOp = 00
PCWrite = 1
PCSource = 00
Outputs?
Fall 2014, Sep
ELEC / Lecture 5

45. State 1: Instr. Decode/Reg. Fetch/ Branch Address (CC2)
PCSource
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALUSrcA=0
ALU
ALUSrcB=11
ALUOut Reg.
IorD
Data
Mem. Data (MDR)
B Reg.
out
RegDst
MUX
control
Add
IRWrite 4
in1
in2
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALUOp
= 00
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

46. State 1 Control FSM Outputs
Start
State 1
Instruction decode (ID) /
Register fetch /
Branch addr.
State0
Instruction
fetch
(IF)
MemRead =1
ALUSrcA = 0
IorD = 0
IRWrite = 1
ALUSrcB = 01
ALUOp = 00
PCWrite = 1
PCSource = 00
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Opcode =
lw, sw
Opcode =
R-type
Opcode
= BEQ
Opcode = J-type
FSM-M
FSM-R
FSM-B
FSM-J
Fall 2014, Sep
ELEC / Lecture 5

47. State 1 (Opcode = lw) → FSM-M (CC3-5)
PCSource
CC4
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite=1
21-25
28-31
16-20
CC3 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALUSrcA=1
ALU
ALUSrcB=10
ALUOut Reg.
IorD=1
Data
Mem. Data (MDR)
B Reg.
out
CC5
MUX
control
Add
IRWrite 4
RegDst=0
in1
in2
MemRead=1
Sign
extend
Shift
left 2
MemtoReg=1
0-15
MemWrite
ALUOp
= 00
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

48. State 1 (Opcode= sw)→FSM-M (CC3-4)
PCSource
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20
CC3 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALUSrcA=1
ALU
ALUSrcB=10
ALUOut Reg.
IorD=1
Data
Mem. Data (MDR)
B Reg.
out
RegDst=0
MUX
control
Add
IRWrite 4
CC4
in1
in2
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite=1
ALUOp
= 00
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

49. FSM-M (Memory Access) From state 1 Opcode = “lw” or “sw” Opcode = “lw”
Compute mem
addrress
ALUSrcA =1
ALUSrcB = 10
ALUOp = 00
Opcode
= “lw”
Opcode
= “sw”
Read
Memory data
Write
memory
MemRead = 1
IorD = 1
MemWrite = 1
IorD = 1
Write
register
To state 0
(Instr. Fetch)
RegWrite = 1
MemtoReg = 1
RegDst = 0
Fall 2014, Sep
ELEC / Lecture 5

50. State 1(Opcode=R-type)→FSM-R (CC3-4)
PCSource
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALU
CC3
ALUSrcA=1
ALUSrcB=00
ALUOut Reg.
11-15
IorD
Data
Mem. Data (MDR)
B Reg.
out
RegDst=0
MUX
control
IRWrite 4
“funct. code”
CC4
in1
in2
MemRead
Sign
extend
Shift
left 2
MemtoReg=0
0-15
MemWrite
ALUOp
= 10
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

51. FSM-R (R-type Instruction)
From state 1 Opcode = R-type
ALU
operation
ALUSrcA =1
ALUSrcB = 00
ALUOp = 10
Write
register
To state 0
(Instr. Fetch)
RegWrite = 1
MemtoReg = 0
RegDst = 1
Fall 2014, Sep
ELEC / Lecture 5

52. State 1 (Opcode = beq ) → FSM-B (CC3)
If(zero)
PCSource 01
PCWrite
etc.=1
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALUSrcA=1
ALU
CC3
ALUSrcB=00
ALUOut Reg.
11-15
IorD
Data
Mem. Data (MDR)
B Reg.
zero
out
RegDst
MUX
control
IRWrite 4
subtract
in1
in2
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALUOp
= 01
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

53. Write PC on “zero” zero=1 PCWriteCond=1 PCWrite etc.=1 PCWrite
PCWrite = 1, unconditionally write PC
Cycle 1, fetch
Cycle 3, jump
Fall 2014, Sep
ELEC / Lecture 5

54. FSM-B (Branch) From state 1 Opcode = “beq” To state 0 (Instr. Fetch)
Write PC on
branch condition
Branch condition:
If A – B=0
zero = 1
ALUSrcA =1
ALUSrcB = 00
ALUOp = 01
PCWriteCond=1
PCSource=01
To state 0
(Instr. Fetch)
Fall 2014, Sep
ELEC / Lecture 5

55. State 1 (Opcode = j) → FSM-J (CC3)
PCSource 10
PCWrite
etc.
Shift
left 2
26-31 to
Control
FSM
0-25
RegWrite
21-25
28-31
16-20 PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALU
ALUSrcA
ALUOut Reg.
11-15
IorD
ALUSrcB
Data
Mem. Data (MDR)
B Reg.
zero
out
RegDst
MUX
control
IRWrite 4
in1
in2
MemRead
Sign
extend
Shift
left 2
MemtoReg
0-15
MemWrite
ALUOp
ALU
control
0-5
Fall 2014, Sep
ELEC / Lecture 5

56. Write PC zero PCWriteCond PCWrite etc.=1 PCWrite=1
PCWrite = 1, unconditionally write PC
Cycle 1, fetch
Cycle 3, jump
Fall 2014, Sep
ELEC / Lecture 5

57. FSM-J (Jump) From state 1 Opcode = “jump” To state 0 (Instr. Fetch)
Write
jump addr. In PC
PCWrite=1
PCSource=10
To state 0
(Instr. Fetch)
Fall 2014, Sep
ELEC / Lecture 5

58. Control FSM Start State 0 1 Instr. fetch/ adv. PC lw or sw J R B 3 2
decode/reg.
fetch/branch
addr.
lw or sw J R B 3 2
Read
memory
data
Compute
memory
addr.
ALU
operation
Write
jump addr.
to PC
Write PC
on branch
condition lw 6 8 9 sw 4 5
Write
register
Write
memory
data 7
Write
register
Fall 2014, Sep
ELEC / Lecture 5

59. Control FSM (Controller)
6 inputs
(opcode)
16 control
outputs
Combinational
logic
Present
state
Next
state
Reset
Clock FF FF FF FF
Fall 2014, Sep
ELEC / Lecture 5

60. Designing the Control FSM
Encode states; need 4 bits for 10 states, e.g.,
State 0 is 0000, state 1 is 0001, and so on.
Write a truth table for combinational logic:
Opcode Present state Control signals Next state
Synthesize a logic circuit from the truth table.
Connect four flip-flops between the next state outputs and present state inputs.
Fall 2014, Sep
ELEC / Lecture 5

61. Block Diagram of a Processor
MemWrite
MemRead
Controller
(Control FSM)
ALU
control
ALUOp
2-bits
Opcode
6-bits
PCSource
2-bits
funct.
[0,5]
ALUOp
3-bits
zero
ALUSrcA
ALUSrcB
2-bits
RegWrite
IorD
Overflow
RegDst
MemtoReg
IRWrite
PCWrite
PCWriteCond
Reset
Clock
Datapath
(PC, register file, registers, ALU)
Mem. Addr.
Mem. write data
Mem. data out
Fall 2014, Sep
ELEC / Lecture 5

62. Exceptions or Interrupts
Conditions under which the processor may produce incorrect result or may “hang”.
Illegal or undefined opcode.
Arithmetic overflow, divide by zero, etc.
Out of bounds memory address.
EPC: 32-bit register holds the affected instruction address.
Cause: 32-bit register holds an encoded exception type. For example,
0 for undefined instruction
1 for arithmetic overflow
Fall 2014, Sep
ELEC / Lecture 5

63. Implementing Exceptions
PCSource 11
(hex)
PCWrite
etc.=1
26-31 to
Control
FSM PC
Instr. reg. (IR)
EPCWrite=1
ALUSrcA=0
ALU
ALUSrcB=01
EPC
CauseWrite=1
Overflow to
Control FSM
out
MUX
control 4
Cause 1
Subtract
in1
in2
32-bit
register
ALUOp
=01
ALU
control
Fall 2014, Sep
ELEC / Lecture 5

64. How Long Does It Take? Again
Assume control logic is fast and does not affect the critical timing. Major time components are ALU, memory read/write, and register read/write.
Time for hardware operations, suppose
Memory read or write 2ns
Register read 1ns
ALU operation 2ns
Register write 1ns
Fall 2014, Sep
ELEC / Lecture 5

65. Single-Cycle Datapath
R-type ns
Load word (I-type) 8ns
Store word (I-type) 7ns
Branch on equal (I-type) 5ns
Jump (J-type) 2ns
Clock cycle time = 8ns
Each instruction takes one cycle
Fall 2014, Sep
ELEC / Lecture 5

66. Performance Parameters
Average cycles per instruction (CPI)
Cycle time (clock period, T)
Execution time of a program
For single-cycle datapath:
CPI = 1
T = hardware time for lw instruction
= T × CPI × (Total instructions executed)
Fall 2014, Sep
ELEC / Lecture 5

67. Multicycle Datapath
Clock cycle time is determined by the longest operation, ALU or memory:
Clock cycle time = 2ns
Cycles per instruction:
lw (10ns)
sw (8ns)
R-type 4 (8ns)
beq (6ns)
j (6ns)
Fall 2014, Sep
ELEC / Lecture 5

68. CPI of a Multicycle Computer
∑k (Instructions of type k) × CPIk
CPI = ——————————————
∑k (instructions of type k)
where
CPIk = Cycles for instruction of type k
Note: CPI is dependent on the instruction mix of the
program being run. Standard benchmark programs
are used for specifying the performance of CPUs.
Fall 2014, Sep
ELEC / Lecture 5

69. Example Consider a program containing:
loads 25%
stores 10%
branches 11%
jumps 2%
Arithmetic 52%
CPI = 0.25× × × × ×4
= 4.12 for multicycle datapath
CPI = 1.00 for single-cycle datapath
Fall 2014, Sep
ELEC / Lecture 5

70. Multicycle vs. Single-Cycle
Performance ratio = Single cycle time / Multicycle time
(CPI × cycle time) for single-cycle
= ———————————————
(CPI × cycle time) for multicycle
1.00 × 8ns
= ————— = 0.97
4.12 × 2ns
Single cycle is faster in this case, but is it always so?
Fall 2014, Sep
ELEC / Lecture 5

71. Consider Another Example
For this program:
loads 5%
stores 5%
branches 30%
jumps 10%
Arithmetic 50%
CPI = 0.05× × × × ×4
= 3.65 for multicycle datapath
CPI = 1.00 for single-cycle datapath
Fall 2014, Sep
ELEC / Lecture 5

72. Multicycle vs. Single-Cycle
Performance ratio = Single cycle time / Multicycle time
(CPI × cycle time) for single-cycle
= ———————————————
(CPI × cycle time) for multicycle
1.00 × 8ns
= ————— = 1.096
3.65 × 2ns
Multicycle is faster in this case, so the performance ratio
depends on the instruction mix. Can we do better?
Fall 2014, Sep
ELEC / Lecture 5

73. Next: Pipelining https://www.youtube.com/watch?v=IjarLbD9r30
Fall 2014, Sep
ELEC / Lecture 5