Test Slab Status CALICE ECAL test slab: what is it all about?

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Presentation transcript:

Test Slab Status CALICE ECAL test slab: what is it all about? Current slab status Outlook and plans 12-07-2007 CALICE Electronics, CERN

Test Slab Overview clock, controls, power data ~1500mm very front-end (VFE) chips sensors front-end (FE) board + chip Single side of a slab Investigate signal transmission over slab lengths over 1.5m clock, data, fast & slow control signals Try to estimate limits imposed by the slab PCB clock distribution, data rate, power consumption Gain experience with the current readout architecture 12-07-2007 CALICE Electronics, CERN

Test Slab Design Thin PCB, <800 mum, 8 copper layers Parallel striplines for differential signal transmission Inter-Panel Bridging Pads Straightforward panel-panel connections Many options for signal routing and readout architectures Mounting Rail Alignment Pins 12-07-2007 CALICE Electronics, CERN

Test Slab Setup slab panel 0: terminator board: resistors + wire bridges slab panel 0: FPGA chips emulating 2 front-end chips each Long, folded PCB traces for pulse transmission measurements End-Of-Slab board: Commercial Starter Kit board FPGA with Rx firmware Clock generators Connection to PC (ethernet) Measurement control firmware intermediate board: power regulators and distribution towards slab panel programmable clock distribution scheme and clock drivers 12-07-2007 CALICE Electronics, CERN

Current Slab Status Bit Error Rate automated measurement pulse transmission along 1.8m folded tracks: v = 0.4*c, attenuation = 20% (2 dB) Bit Error Rate automated measurement resolution of 10-5 dummy wires vs. loop-back slab traces including clock distribution system latest: with external DHCAL pVFE 12-07-2007 CALICE Electronics, CERN

Current Slab Status II & Plans Implemented DHCAL VHDL in slab FPGA N=1 OK, N=2 OK, now N=N+1 Extend setup by adding slab panels Determine transmission speed limits on PCB traces Investigate power consumption for transmission paths along full slab length, both for CMOS and LVDS Implement/study alternative readout architecture 12-07-2007 CALICE Electronics, CERN