Flip Flops

Clock Signal Sequential logic circuits have memory Output is a function of input and present state Sequential circuits are synchronized by a periodic “clock” signal

Clock Signal generator Clock signals can be generated using odd number of inverters

Flip Flop A basic sequential circuit is a flip-flop Flip-flop has two stable states of complementary output values

SR Flip Flop SR (set-reset) flip-flop based on two nor gates

SR Flip Flop

Noise Reduction in SR Flip Flop SR flip flop can reduce a switching noise When switch is pulled down some oscillations may occur at B They will be eliminated by the flip-flop

Exercise For a given S and R inputs to SR flip-flop, sketch the output signal Q Q t

Exercise

SR Flip Flop SR (set-reset) flip-flop based on two nand gates

Clocked SR Flip Flop Circuit Clock controlled flip-flop changes its state only when the clock C is high

Clocked SR Flip Flop Circuit with Reset Some flip-flops have asynchronous preset Pr and clear Cl signals. Output changes once these signals change, however the input signals must wait for a change in clock to change the output

Edge Triggered Flip Flop Edge triggered flip-flop changes only when the clock C changes

Positive Edge Triggered Flip Flop Positive-edge triggered flip-flop changes only on the rising edge of the clock C

Exercise The input D to a positive-edge triggered flip-flop is shown Find the output signal Q Q t

Exercise

Negative Edge Triggered JK Flip Flop

Other Flip Flops T J D Q f K Delay Flip-Flop Toggle Flip-Flop (D-latch)

Race Problem Q f D 1 t loop Signal can race around during = 1

Master-Slave Flip Flop Implementation Q J K f MASTER SLAVE PRESET CLEAR SI RI Master transmits the signal to the output during the high clock phase and slave is waiting for the clock to change this prevents race conditions

Master-Slave Edge-Triggered Flip-Flop Master-Slave configuration Compared to transistor version MASTER SLAVE D Q CLK CLK 36 Transistors VDD VDD CLK CLK D Q CLK CLK 8 Transistors GND GND

Alternative Edge-Triggered Flip-Flop VDD VDD CLK CLK Q D Q CLK CLK CLK Q GND GND D 24 Transistors 8 Transistors

JK Flip-Flop from D-Latch Same as RS-Latch except “toggle” on 11 J D Latch Q K Q CLK JK-FF J Q CLK J K Q 0 X X No change CLK 1 0 0 No change K 1 0 1 1 1 0 1 1 1 1 Toggle

Toggle Flip-Flop from D-Latch Toggles stored value if T = 1 when CLK is high D Latch Q T CLK CLK T Q T T-FF Q 0 X No change 1 0 No change CLK 1 1 Toggle

END