1. EEE2243 Digital System Design Chapter 2: Sequential Logic Recap by Muhazam Mustapha, January 2011

2. Learning Outcome
By the end of this chapter, students are expected to refresh their knowledge on sequential logic related to HDL

3. Chapter Content
Sequential Logic
Methodologies in Sequential Logic

4. Sequential Logic

5. Definition
Sequential logic is the type of digital system that does not only depend on current input, but also the previous history of the system
For that reason sequential logic requires memory elements to function
Sequential systems also require external combinational system to make transitions from state to state
We’ll refresh our memory about sequential logic enough for use with HDL (Verilog)

6. General Block Diagram Input Output Combinational Logic Current State
Next State
Sequential System
Sequential Logic
Clock
Vahid Example 3.11 pg 139

7. Flip-Flops
Flip-flops are the most basic memory elements used in sequential systems
There are 4 elementary flip-flops
A group of flip-flops that are used together to achieve the system functionality is called REGISTER
Difference between flip-flops and latches
Flip-flops are edge triggered
Latches are level triggered
- SR Latches
- JK Flip-Flops
- D Flip-Flops
- T Flip-Flops

8. SR Latch SR latch is the simplest kind of bi-stable memory element
Can be built either by NOR or NAND gates: S S Q Q S Q S Q R Q R Q Q Q R R S R Q
Invalid 1
Stay
Characteristic equation: S R Q
Stay 1
Invalid

9. JK Flip-flop
Can be constructed from SR latch to remove invalid input combination J K Q
Next Q (Q*) 1
Characteristic equation: J Q
clk K Q J S Q
clk K R Q

10. D Flip-flop The most popular flip-flop nowadays
Built with inverted input JK flip-flop
Characteristic equation: D Q D Q Q* 1
clk Q D J Q
clk K Q

11. T Flip-flop JK flip-flop with tied-up inputs
Toggles if T is high, otherwise stays
Characteristic equation: T Q T Q Q* 1
clk Q T J Q
clk K Q

12. Methodoligies in Sequential Logic

13. Triggering Modes Level Triggered Edge Triggered High LevelQ
Positive Edge Q FF FF Q Q
Low Level Q
Negative Edge Q FF FF Q Q
The flip-flop is called latch
The trigger is called clock

14. Clocking Modes Asynchronous Common Global Clock Synchronous D Q D Q D
clk
clk
clk
Asynchronous D Q D Q D Q
clk
clk
clk
Common Global Clock
Synchronous

15. Timing Diagram Trigger Trigger Trigger of more than 1 line change
undefined

16. Setup and Hold Time
Setup: minimum time to allow input to stabilized before clock arrival
So that transition is done on valid inputs
Setup time
Hold time
Hold: minimum time for input to stay stable after clock arrival
So that clock has time to propogate
Vahid §3.5 pg 146

17. Set vs Reset Set (or preset): flip-flop is given a value of 1
Synchronous: the set or reset signal arrives to the flip-flop but the set or reset process only takes place when clock comes
Asynchronous: set or reset process takes place immediately when the signal arrives regardless of clock FF Q FF Q FF Q FF Q S Q R Q AS Q AR Q
Vahid §3.5 pg 149

18. Finite State Machine
FSM is a behavioral model of digital sequential system
It is defined by a few predetermined states
It is drawn like a flow chart showing transitions between states and what condition triggers it
Two methods of FSM design:
Mealy Machine: output depends on both current state and input
Moore Machine: output depend only on current state
Vahid §3.3 pg 122

19. Mealy Machine
Input
Output

20. Moore Machine