Chapter 1 & Chapter 3.

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Presentation transcript:

Chapter 1 & Chapter 3

Circuit Under Design From Rabaey 2003

Inverter Cross-Section Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Biasing Points (G, D and S) How about the bulk (substrate)? Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

With Substrate Contacts Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Masks Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Photomask in Operation Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Patterning of SiO2 Chemical or plasma etch Si-substrate Hardened resist SiO 2 (a) Silicon base material Si-substrate Photoresist SiO 2 (d) After development and etching of resist, chemical or plasma etch of SiO Si-substrate 2 (b) After oxidation and deposition Hardened resist of negative photoresist SiO 2 Si-substrate UV-light Patterned (e) After etching optical mask Exposed resist SiO 2 Si-substrate Si-substrate (f) Final result after removal of resist (c) Stepper exposure From Rabaey 2003

CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers From Rabaey 2003

P-Type Substrate and N-Well PMOS devices go here P-type substrate NMOS devices go here N-well mask slides on mask sequence by Jay Brockman – Univ. notre Dame From Rabaey 2003

Active Area deposited nitride layer active mask defines p-type and n-type mosfet locations (drain-gate-source) From Rabaey 2003

Field Oxide Growth Thick field oxide electrically isolates transistors Nitride prevents field oxide growth Thin gate oxide grown after nitride removed o2 o2 o2 o2 o2 o2 o2 gate oxide field oxide SiO2 formation consumes Si Si-SiO2 interface below original Si surface From Rabaey 2003

Polysilicon Gate poly mask added to layout From Rabaey 2003

P-Select Mask and N-Type Source/Drain Implant p-select covers p-type source/drain regions select mask must overlap active areas n-type ion implant creates n-type source/drain regions high temperature anneal repairs silicon lattice and causes diffusion of implanted ions From Rabaey 2003

N-Select Mask and P-Type Source/Drain Implant p-type implant finished mosfets both select masks added From Rabaey 2003

Improving Drain and Source Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Contact Cuts Thin oxide Field oxide From Rabaey 2003

Metal 1 non-planar surface From Rabaey 2003

Via 1 and Metal 2 Multilevel interconnect fabrication processes planarize between layers (expensive) MOSIS SCMOS does not allow stacked vias From Rabaey 2003

Sharp Etch Profile for Metal Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Metallization Cross-Section Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Substrate Contacts Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

p+ Substrate Contact Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Final Steps w/ Substrate Contact Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

An Inverter Layout Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

A Standard Cell Layout Why l ? Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Stick Diagram Dimensionless layout entities Only topology is important Final layout generated by “compaction” program Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Color Stick Diagram 1 V 3 In Out GND Dimensionless layout entities Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program From Rabaey 2003

Hypothetical 90nm Tech. Design Rules Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Hypothetical 90nm Technology Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

90 nm Technology Design Example Design Rules 0,15mm 0,1mm 0,15mm l = 0,03mm 0,15mm Design Rules

Design Rules are Followed Alignment Mark Design should be Fine !! l = 0,03mm

Active and Poly Masks Poly Mask Active Mask

Fabricated Transistor (Under Misalignment of 0.06 mm) Alignment Marks Transistor Still Correct !! l = 0,03mm Design Example

Design Rules are Not Followed Alignment Mark Design in Danger !! l = 0,03mm

Active and Poly Masks- 2 Closer Poly Mask Active Mask

Fabricated Transistor (Under Misalignment of 0.06 mm)- 2 Alignment Marks Transistor with Changed W and L !! l = 0,03mm

Design Rules- 1 Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules) Attention: usually, l is half of smallest allowed transistor channel length (L)

Design Rules- 2 Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Routing Tracks Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

nMOS and pMOS Spacing Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOSIS Design Rules mosis.com Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Some Technologies by MOSIS Observe l is the best approximation to the half of the feature size Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOSIS Design Rules Listing Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

MOSIS Design Rules Listing Copyright © 2005 Pearson Addison-Wesley. All rights reserved.

Hypothetical 90nm Tech. Design Rules 3-46 Copyright © 2005 Pearson Addison-Wesley. All rights reserved. 3-46

Hypothetical 90nm Technology Copyright © 2005 Pearson Addison-Wesley. All rights reserved. 3-47