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Topics Design rules and fabrication SCMOS scalable design rules

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Presentation on theme: "Topics Design rules and fabrication SCMOS scalable design rules"— Presentation transcript:

1 Topics Design rules and fabrication SCMOS scalable design rules
Stick diagrams 1

2 Why we need design rules
Masks are tooling for manufacturing. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

3 Manufacturing problems
Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.

4 Transistor problems Variations in threshold voltage:
oxide thickness; ion implantation; poly variations. Changes in source/drain diffusion overlap. Variations in substrate.

5 Wiring problems Diffusion: changes in doping -> variations in resistance, capacitance. Poly, metal: variations in height, width -> variations in resistance, capacitance. Shorts and opens:

6 Oxide problems Variations in height.
Lack of planarity -> step coverage. metal 2 metal 2 metal 1

7 Via problems Via may not be cut all the way through.
Undersize via has too much resistance. Via may be too large and create short.

8  and design rules  is the size of a minimum feature.
Specifying  particularizes the scalable rules. Parasitics are generally not specified in units

9 MOSIS SCMOS design rules
Designed to scale across a wide range of technologies. Designed to support multiple vendors. Designed for educational use. Ergo, fairly conservative.

10 Wires metal 3 6 metal 2 3 metal 1 3 pdiff/ndiff 3 poly 2

11 Transistors 2 2 3 3 1 5

12 Vias Types of via: metal1/diff, metal1/poly, metal1/metal2. 4 4 1 2

13 Tub tie 4 1

14 Spacings Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1
Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4

15 Stick diagrams A stick diagram is a cartoon of a layout.
Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

16 Stick layers metal 3 metal 2 metal 1 poly ndiff pdiff

17 Dynamic latch stick diagram
VDD in out VSS phi phi

18 Layout design and analysis tool
Layout editor Design rule checker (DRC) Circuit extractor 1

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