Hardware Testing and Designing for Testability RTLAB 최치호 2003. 1. 3

Contents TESTING COMBINATIONAL LOGIC TESTING SEQUENTIAL LOGIC SCAN TESTING BOUNDARY SCAN BUILT-IN SELF-TEST

TESTING COMBINATIONAL LOGIC Fault Type Stuck-at-Faults . Stuck-at-0 . Stuck-at-1 2. Bridging Faults . Two unconnected signal lines are shorted together

Testing an AND-OR Network

Example Network for Stuck-at Fault Testing

TESTING SEQUENTIAL LOGIC More difficult than testing combinational logic Use sequences of inputs for testing Way to derive test sequences Iterative Network Based on testing for stuck-at faults

Sequential and Iterative Networks

Based on testing for stuck-at faults

SCAN TESTING Scan Path Test Circuit Using Two-port Flip-flops

System with Flip-flop Registers and Combinational Logic Blocks

BOUNDARY SCAN TAP Test access port

Typical Boundary Scan Cell

Basic Boundary Scan Architecture - BSR (Boundary Scan Register)

BUILT-IN SELF-TEST Digital systems become more and more complex Add logic to the IC so that it can test itself => Built-In Self-Test (BIST) Generic BIST Scheme

Self-test Circuit for RAM with Signature Register Signature register : compress the output data into a short string of bits called a signature MISR : Multiple-Input Signature Register

Modified LFSR with 0000 State 4-bit Linear Feedback Shift Register (LFSR) Multiple-input Signature Register (MISR) Pattern generated are: 1000,1100,1110,1111,0111,1011, 0101,1010,1101,0110,0011,1001, 0100,0010,0001,1000,….

BIST Using BILBO (Built-in logic block observation) Register PRPG : Pseudo random pattern generator, LFSR

4-bit BILBO Register (MIST)

VHDL Code for BILBO Register -- NBITS : The number of bits