EMT 351/4 DIGITAL IC DESIGN Mrs. Siti Zarina Md Naziri

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Presentation transcript:

EMT 351/4 DIGITAL IC DESIGN Mrs. Siti Zarina Md Naziri Subject Coordinator/Lecturer Mrs. Siti Zarina Md Naziri School of Microelectronic Engineering Block A, 1st Floor, Kompleks Pusat Pengajian Jejawi 1 04-979 8386 (O) 012-3225646 (H/P)

Course Outcomes (COs) Students should be able to grasp the hardware and software principles of digital design using Verilog HDL 1 Students should be able to design and simulate a complete digital system consisting of a control unit and datapath unit 2 Students should be able to understand the working principles of the field programmable gate array (FPGA) device 3

Class COMPULSARY !! Attendance? LABS LECTURES MONDAYS 8 am – 10 am 12 pm – 2 pm 4 pm – 6 pm TUESDAYS 8 am – 10 am (DKP3) Attendance? COMPULSARY !! FRIDAYS 4.30 pm – 5.30 pm (DKR4) THURSDAYS 8 am – 10 am 4 pm – 6 pm

Grading 100%! 50% 10% 20% 10% 10% TOTAL OF FINAL EXAM TESTS MINI PROJECT 10% QUIZ / ASSIGNMENTS 10% LAB (TOTAL OF 5 LABS)

Main References 1 MAIN TEXT “Starter's guide to Verilog 2001” / Michael D. Ciletti. Pearson/Prentice Hall, 2004 “Verilog 2001 for Beginners” (compiled by Norina Idris, Siti Zarina Md Naziri, Rizalafande Che Ismail et al.) / Michael D. Ciletti. Pearson/Prentice Hall, 2008 OUR NEW MAIN TEXT.. SOON!! 2

Additional References 1 GOOD TEXT.. "Verilog HDL, A Guide To Digital Design And Synthesis” / Samir Palnitkar, Prentice Hall, 2003. “Modeling, Synthesis and Rapid Prototyping with the Verilog HDL” / Michael D. Ciletti, Prentice Hall, 1999. MORE ADVANCED TEXT 2

Course Outline StudyWeek Session Content 1 Lecture EDA and HDL EDA, HDL, The Role and Requirements of HDLs in EDA, Benefits of Using HDLs in EDA. 2 Hardware Modeling Hardware Modeling: Verilog Primitives, Descriptive Styles, Structural Connections, Behavioural Descriptions, Hierarchical Descriptions of Hardware, Structured (Top-Down) Design Methodology, Language Conventions, Representation of Numbers. 3 Lab: Lab 1 Event-Driven Simulation And Testbenches Simulation with Verilog and Design Unit Testbench. 4 Lab: Lab 2 Tutorial #1 Logic System, Data Types, And Operators Variables, Logic Value Set, Data Types, Constants, Operators, Expressions and Operands, and Operator Precedence.

Course Outline 5 Lecture Lab: Lab 3 User-Defined Primitives Combinational Behavior and Sequential Behavior. 6 Lab: Lab 4 Test #1 Propagation Delay Built-In Constructs for Delay, Signal Transitions, Verilog Models for Gate Propagation Delay (Inertial Delay), Module Paths and Delays. 7 CUTI PERTENGAHAN SEMESTER/MID SEMESTER BREAK 8, 9, 10 Lab: Lab 5 Lab: Mini Project Behavioural Descriptions Verilog Behaviors, Behavioural Statements, Intra-Assignment Delay: Blocking Assignments and Non-Blocking Assignment, Indeterminate Assignments and Ambiguity, Constructs For Activity Flow Control – Conditional Operator, Case statement, Conditional statement (if..else), loops: for, while, forever, always, Tasks and Functions, Behavioural Models of Finite State Machines.

Course Outline 11,12 Lecture Lab: Mini Project Tutorial #2 Logic Synthesis with Verilog HDL Definition, Impact of Logic Synthesis, Verilog HDL Synthesis. 13 Test #2 Switch-Level Models MOS Transistor Technology, Switch-Level Models of MOS Transistors and Static CMOS Circuits, CMOS Transmission Gates (Switches). 14 Lab: Mini Project (Viva & Report Submission) Rapid Prototyping With FPGAs Introduction To FPGAs, Role of FPGAs In The ASIC Market, FPGA Technologies, Rapid Prototyping With Verilog and FPGAs. 15 MINGGU ULANGKAJI / REVISION WEEK